upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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205 lines
3.8 KiB
205 lines
3.8 KiB
/*
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* SPDX-License-Identifier: GPL-2.0 IBM-pibs
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*/
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/*----------------------------------------------------------------------------- */
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/* Function: ext_bus_cntlr_init */
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/* Description: Initializes the External Bus Controller for the external */
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/* peripherals. IMPORTANT: For pass1 this code must run from */
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/* cache since you can not reliably change a peripheral banks */
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/* timing register (pbxap) while running code from that bank. */
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/* For ex., since we are running from ROM on bank 0, we can NOT */
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/* execute the code that modifies bank 0 timings from ROM, so */
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/* we run it from cache. */
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/* Bank 0 - Flash and SRAM */
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/* Bank 1 - NVRAM/RTC */
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/* Bank 2 - Keyboard/Mouse controller */
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/* Bank 3 - IR controller */
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/* Bank 4 - not used */
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/* Bank 5 - not used */
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/* Bank 6 - not used */
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/* Bank 7 - FPGA registers */
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/*----------------------------------------------------------------------------- */
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#include <asm/ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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.globl write_without_sync
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write_without_sync:
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/*
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* Write one values to host via pci busmastering
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* ptr = 0xc0000000 -> 0x01000000 (PCI)
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* *ptr = 0x01234567;
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*/
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addi r31,0,0
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lis r31,0xc000
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start1:
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lis r0,0x0123
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ori r0,r0,0x4567
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stw r0,0(r31)
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/*
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* Read one value back
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* ptr = (volatile unsigned long *)addr;
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* val = *ptr;
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*/
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lwz r0,0(r31)
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/*
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* One pci config write
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* ibmPciConfigWrite(0x2e, 2, 0x1234);
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*/
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/* subsystem id */
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li r4,0x002C
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oris r4,r4,0x8000
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lis r3,0xEEC0
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stwbrx r4,0,r3
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li r5,0x1234
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ori r3,r3,0x4
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stwbrx r5,0,r3
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b start1
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blr /* never reached !!!! */
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.globl write_with_sync
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write_with_sync:
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/*
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* Write one values to host via pci busmastering
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* ptr = 0xc0000000 -> 0x01000000 (PCI)
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* *ptr = 0x01234567;
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*/
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addi r31,0,0
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lis r31,0xc000
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start2:
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lis r0,0x0123
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ori r0,r0,0x4567
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stw r0,0(r31)
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/*
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* Read one value back
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* ptr = (volatile unsigned long *)addr;
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* val = *ptr;
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*/
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lwz r0,0(r31)
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/*
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* One pci config write
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* ibmPciConfigWrite(0x2e, 2, 0x1234);
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*/
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/* subsystem id */
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li r4,0x002C
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oris r4,r4,0x8000
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lis r3,0xEEC0
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stwbrx r4,0,r3
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sync
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li r5,0x1234
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ori r3,r3,0x4
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stwbrx r5,0,r3
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sync
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b start2
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blr /* never reached !!!! */
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.globl write_with_less_sync
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write_with_less_sync:
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/*
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* Write one values to host via pci busmastering
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* ptr = 0xc0000000 -> 0x01000000 (PCI)
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* *ptr = 0x01234567;
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*/
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addi r31,0,0
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lis r31,0xc000
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start2b:
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lis r0,0x0123
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ori r0,r0,0x4567
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stw r0,0(r31)
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/*
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* Read one value back
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* ptr = (volatile unsigned long *)addr;
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* val = *ptr;
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*/
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lwz r0,0(r31)
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/*
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* One pci config write
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* ibmPciConfigWrite(0x2e, 2, 0x1234);
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*/
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/* subsystem id */
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li r4,0x002C
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oris r4,r4,0x8000
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lis r3,0xEEC0
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stwbrx r4,0,r3
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sync
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li r5,0x1234
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ori r3,r3,0x4
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stwbrx r5,0,r3
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/* sync */
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b start2b
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blr /* never reached !!!! */
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.globl write_with_more_sync
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write_with_more_sync:
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/*
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* Write one values to host via pci busmastering
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* ptr = 0xc0000000 -> 0x01000000 (PCI)
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* *ptr = 0x01234567;
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*/
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addi r31,0,0
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lis r31,0xc000
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start3:
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lis r0,0x0123
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ori r0,r0,0x4567
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stw r0,0(r31)
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sync
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/*
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* Read one value back
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* ptr = (volatile unsigned long *)addr;
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* val = *ptr;
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*/
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lwz r0,0(r31)
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sync
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/*
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* One pci config write
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* ibmPciConfigWrite(0x2e, 2, 0x1234);
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*/
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/* subsystem id (PCIC0_SBSYSVID)*/
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li r4,0x002C
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oris r4,r4,0x8000
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lis r3,0xEEC0
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stwbrx r4,0,r3
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sync
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li r5,0x1234
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ori r3,r3,0x4
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stwbrx r5,0,r3
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sync
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b start3
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blr /* never reached !!!! */
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