upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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241 lines
6.4 KiB
241 lines
6.4 KiB
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2007
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*
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* Author: Scott Wood <scottwood@freescale.com>,
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* with some bits from older board-specific PCI initialization.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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#include <asm/mpc8349_pci.h>
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#define MAX_BUSES 2
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DECLARE_GLOBAL_DATA_PTR;
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static struct pci_controller pci_hose[MAX_BUSES];
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static int pci_num_buses;
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static void pci_init_bus(int bus, struct pci_region *reg)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile pot83xx_t *pot = immr->ios.pot;
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volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
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struct pci_controller *hose = &pci_hose[bus];
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u32 dev;
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u16 reg16;
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int i;
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if (bus == 1)
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pot += 3;
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/* Setup outbound translation windows */
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for (i = 0; i < 3; i++, reg++, pot++) {
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if (reg->size == 0)
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break;
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hose->regions[i] = *reg;
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hose->region_count++;
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pot->potar = reg->bus_start >> 12;
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pot->pobar = reg->phys_start >> 12;
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pot->pocmr = ~(reg->size - 1) >> 12;
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if (reg->flags & PCI_REGION_IO)
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pot->pocmr |= POCMR_IO;
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#ifdef CONFIG_83XX_PCI_STREAMING
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else if (reg->flags & PCI_REGION_PREFETCH)
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pot->pocmr |= POCMR_SE;
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#endif
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if (bus == 1)
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pot->pocmr |= POCMR_DST;
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pot->pocmr |= POCMR_EN;
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}
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/* Point inbound translation at RAM */
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pci_ctrl->pitar1 = 0;
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pci_ctrl->pibar1 = 0;
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pci_ctrl->piebar1 = 0;
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pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
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i = hose->region_count++;
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hose->regions[i].bus_start = 0;
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hose->regions[i].phys_start = 0;
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hose->regions[i].size = gd->ram_size;
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hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
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hose->first_busno = pci_last_busno() + 1;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
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CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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#ifndef CONFIG_PCISLAVE
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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/*
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* The caller must have already set OCCR, and the PCI_LAW BARs
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* must have been set to cover all of the requested regions.
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*
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* If fewer than three regions are requested, then the region
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* list is terminated with a region of size 0.
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*/
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void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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int i;
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if (num_buses > MAX_BUSES) {
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printf("%d PCI buses requsted, %d supported\n",
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num_buses, MAX_BUSES);
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num_buses = MAX_BUSES;
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}
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pci_num_buses = num_buses;
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/*
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* Release PCI RST Output signal.
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* Power on to RST high must be at least 100 ms as per PCI spec.
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* On warm boots only 1 ms is required, but we play it safe.
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*/
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udelay(100000);
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for (i = 0; i < num_buses; i++)
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immr->pci_ctrl[i].gcr = 1;
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/*
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* RST high to first config access must be at least 2^25 cycles
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* as per PCI spec. This could be cut in half if we know we're
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* running at 66MHz. This could be insufficiently long if we're
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* running the PCI bus at significantly less than 33MHz.
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*/
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udelay(1020000);
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for (i = 0; i < num_buses; i++)
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pci_init_bus(i, reg[i]);
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}
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#ifdef CONFIG_PCISLAVE
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#define PCI_FUNCTION_CONFIG 0x44
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#define PCI_FUNCTION_CFG_LOCK 0x20
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/*
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* Unlock the configuration bit so that the host system can begin booting
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*
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* This should be used after you have:
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* 1) Called mpc83xx_pci_init()
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* 2) Set up your inbound translation windows to the appropriate size
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*/
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void mpc83xx_pcislave_unlock(int bus)
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{
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struct pci_controller *hose = &pci_hose[bus];
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u32 dev;
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u16 reg16;
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/* Unlock configuration lock in PCI function configuration register */
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
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reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
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pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
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/* The configuration bit is now unlocked, so we can scan the bus */
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT)
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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int nodeoffset;
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int tmp[2];
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const char *path;
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if (pci_num_buses < 1)
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return;
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nodeoffset = fdt_path_offset(blob, "/aliases");
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if (nodeoffset >= 0) {
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path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
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tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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if (pci_num_buses < 2)
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return;
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path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
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tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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}
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}
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#endif /* CONFIG_OF_LIBFDT */
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