upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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296 lines
9.6 KiB
296 lines
9.6 KiB
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_srio.h>
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#define SRIO_PORT_ACCEPT_ALL 0x10000001
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#define SRIO_IB_ATMU_AR 0x80f55000
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#define SRIO_OB_ATMU_AR_MAINT 0x80077000
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#define SRIO_OB_ATMU_AR_RW 0x80045000
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#define SRIO_LCSBA1CSR_OFFSET 0x5c
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#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
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#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
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#define SRIO_LCSBA1CSR 0x60000000
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#if defined(CONFIG_FSL_CORENET)
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#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
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#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
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#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#elif defined(CONFIG_MPC85xx)
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#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
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#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
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#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#elif defined(CONFIG_MPC86xx)
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#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
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#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
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#define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
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(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
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#else
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#error "No defines for DEVDISR_SRIO"
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#endif
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void srio_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
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int srio1_used = 0, srio2_used = 0;
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if (is_serdes_configured(SRIO1)) {
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set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
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law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
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LAW_TRGT_IF_RIO_1);
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srio1_used = 1;
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printf("SRIO1: enabled\n");
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} else {
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printf("SRIO1: disabled\n");
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}
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#ifdef CONFIG_SRIO2
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if (is_serdes_configured(SRIO2)) {
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set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
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law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
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LAW_TRGT_IF_RIO_2);
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srio2_used = 1;
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printf("SRIO2: enabled\n");
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} else {
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printf("SRIO2: disabled\n");
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}
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#endif
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#ifdef CONFIG_FSL_CORENET
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/* On FSL_CORENET devices we can disable individual ports */
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if (!srio1_used)
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
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if (!srio2_used)
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
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#endif
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/* neither port is used - disable everything */
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if (!srio1_used && !srio2_used) {
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setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
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setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
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setbits_be32(&gur->devdisr, _DEVDISR_RMU);
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}
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}
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#ifdef CONFIG_SRIOBOOT_MASTER
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void srio_boot_master(void)
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{
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struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
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/* set port accept-all */
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out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
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SRIO_PORT_ACCEPT_ALL);
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debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
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CONFIG_SRIOBOOT_MASTER_PORT);
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/* configure inbound window for slave's u-boot image */
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debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
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"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
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(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
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(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
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CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
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CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
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CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
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/* configure inbound window for slave's u-boot image */
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debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
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"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
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(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
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(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
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CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
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CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
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CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
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/* configure inbound window for slave's ucode */
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debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
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"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
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(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
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(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
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CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
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CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
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CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
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/* configure inbound window for slave's ENV */
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debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; "
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"Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n",
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CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
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CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
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CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
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CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
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CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
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}
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#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
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void srio_boot_master_release_slave(void)
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{
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struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
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u32 escsr;
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debug("SRIOBOOT - MASTER: "
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"Check the port status and release slave core ...\n");
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escsr = in_be32((void *)&srio->lp_serial
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.port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
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if (escsr & 0x2) {
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if (escsr & 0x10100) {
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debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
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CONFIG_SRIOBOOT_MASTER_PORT);
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} else {
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debug("SRIOBOOT - MASTER: "
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"Port [ %d ] is ready, now release slave's core ...\n",
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CONFIG_SRIOBOOT_MASTER_PORT);
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/*
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* configure outbound window
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* with maintenance attribute to set slave's LCSBA1CSR
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*/
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[1].rowtar, 0);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[1].rowtear, 0);
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if (CONFIG_SRIOBOOT_MASTER_PORT)
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[1].rowbar,
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CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
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else
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[1].rowbar,
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CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[1].rowar,
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SRIO_OB_ATMU_AR_MAINT
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| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
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/*
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* configure outbound window
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* with R/W attribute to set slave's BRR
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*/
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[2].rowtar,
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SRIO_LCSBA1CSR >> 9);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[2].rowtear, 0);
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if (CONFIG_SRIOBOOT_MASTER_PORT)
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[2].rowbar,
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(CONFIG_SYS_SRIO2_MEM_PHYS
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+ SRIO_MAINT_WIN_SIZE) >> 12);
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else
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[2].rowbar,
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(CONFIG_SYS_SRIO1_MEM_PHYS
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+ SRIO_MAINT_WIN_SIZE) >> 12);
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out_be32((void *)&srio->atmu
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.port[CONFIG_SRIOBOOT_MASTER_PORT]
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.outbw[2].rowar,
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SRIO_OB_ATMU_AR_RW
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| atmu_size_mask(SRIO_RW_WIN_SIZE));
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/*
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* Set the LCSBA1CSR register in slave
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* by the maint-outbound window
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*/
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if (CONFIG_SRIOBOOT_MASTER_PORT) {
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out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
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+ SRIO_LCSBA1CSR_OFFSET,
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SRIO_LCSBA1CSR);
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while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
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+ SRIO_LCSBA1CSR_OFFSET)
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!= SRIO_LCSBA1CSR)
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;
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/*
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* And then set the BRR register
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* to release slave core
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*/
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out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
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+ SRIO_MAINT_WIN_SIZE
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+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
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CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
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} else {
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out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
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+ SRIO_LCSBA1CSR_OFFSET,
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SRIO_LCSBA1CSR);
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while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
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+ SRIO_LCSBA1CSR_OFFSET)
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!= SRIO_LCSBA1CSR)
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;
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/*
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* And then set the BRR register
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* to release slave core
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*/
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out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
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+ SRIO_MAINT_WIN_SIZE
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+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
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CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
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}
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debug("SRIOBOOT - MASTER: "
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"Release slave successfully! Now the slave should start up!\n");
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}
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} else
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debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n",
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CONFIG_SRIOBOOT_MASTER_PORT);
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}
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#endif
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#endif
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