upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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197 lines
4.8 KiB
197 lines
4.8 KiB
/*
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* (C) Copyright 2016
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/gpio.h>
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#include <dm/platdata.h>
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#include <dm/platform_data/serial_stm32x7.h>
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#include <asm/arch/stm32_periph.h>
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#include <asm/arch/stm32_defs.h>
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#include <asm/arch/syscfg.h>
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DECLARE_GLOBAL_DATA_PTR;
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const struct stm32_gpio_ctl gpio_ctl_gpout = {
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.mode = STM32_GPIO_MODE_OUT,
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.otype = STM32_GPIO_OTYPE_PP,
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.speed = STM32_GPIO_SPEED_50M,
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.pupd = STM32_GPIO_PUPD_NO,
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.af = STM32_GPIO_AF0
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};
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const struct stm32_gpio_ctl gpio_ctl_fmc = {
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.mode = STM32_GPIO_MODE_AF,
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.otype = STM32_GPIO_OTYPE_PP,
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.speed = STM32_GPIO_SPEED_100M,
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.pupd = STM32_GPIO_PUPD_NO,
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.af = STM32_GPIO_AF12
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};
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static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
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/* Chip is LQFP144, see DM00077036.pdf for details */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
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{STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
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{STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */
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{STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
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};
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static int fmc_setup_gpio(void)
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{
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int rv = 0;
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int i;
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clock_setup(GPIO_B_CLOCK_CFG);
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clock_setup(GPIO_C_CLOCK_CFG);
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clock_setup(GPIO_D_CLOCK_CFG);
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clock_setup(GPIO_E_CLOCK_CFG);
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clock_setup(GPIO_F_CLOCK_CFG);
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clock_setup(GPIO_G_CLOCK_CFG);
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clock_setup(GPIO_H_CLOCK_CFG);
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for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
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rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
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&gpio_ctl_fmc);
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if (rv)
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goto out;
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}
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out:
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return rv;
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}
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int dram_init(void)
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{
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int rv;
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rv = fmc_setup_gpio();
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if (rv)
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return rv;
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clock_setup(FMC_CLOCK_CFG);
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stm32_sdram_init();
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/*
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* Fill in global info with description of SRAM configuration
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
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gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
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gd->ram_size = CONFIG_SYS_RAM_SIZE;
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return rv;
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}
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int uart_setup_gpio(void)
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{
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clock_setup(GPIO_A_CLOCK_CFG);
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clock_setup(GPIO_B_CLOCK_CFG);
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return 0;
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}
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#ifdef CONFIG_ETH_DESIGNWARE
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static int stmmac_setup(void)
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{
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clock_setup(SYSCFG_CLOCK_CFG);
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/* Set >RMII mode */
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STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
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clock_setup(GPIO_A_CLOCK_CFG);
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clock_setup(GPIO_C_CLOCK_CFG);
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clock_setup(GPIO_G_CLOCK_CFG);
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clock_setup(STMMAC_CLOCK_CFG);
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return 0;
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}
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#endif
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#ifdef CONFIG_STM32_QSPI
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static int qspi_setup(void)
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{
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clock_setup(GPIO_B_CLOCK_CFG);
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clock_setup(GPIO_D_CLOCK_CFG);
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clock_setup(GPIO_E_CLOCK_CFG);
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return 0;
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}
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#endif
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u32 get_board_rev(void)
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{
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return 0;
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}
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int board_early_init_f(void)
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{
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int res;
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res = uart_setup_gpio();
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if (res)
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return res;
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#ifdef CONFIG_ETH_DESIGNWARE
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res = stmmac_setup();
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if (res)
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return res;
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#endif
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#ifdef CONFIG_STM32_QSPI
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res = qspi_setup();
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if (res)
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return res;
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#endif
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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