upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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179 lines
4.8 KiB
179 lines
4.8 KiB
/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _ASM_ARCH_ARMADA100_H
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#define _ASM_ARCH_ARMADA100_H
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#include <asm/io.h>
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#endif /* __ASSEMBLY__ */
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#if defined (CONFIG_ARMADA100)
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#include <asm/arch/cpu.h>
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
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#define APBC_RST (1<<2) /* Reset Generation */
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/* Functional Clock Selection Mask */
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#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
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/* Fast Ethernet Controller Clock register definition */
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#define FE_CLK_RST 0x1
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#define FE_CLK_ENA 0x8
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/* Register Base Addresses */
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#define ARMD1_DRAM_BASE 0xB0000000
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#define ARMD1_FEC_BASE 0xC0800000
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#define ARMD1_TIMER_BASE 0xD4014000
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#define ARMD1_APBC1_BASE 0xD4015000
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#define ARMD1_APBC2_BASE 0xD4015800
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#define ARMD1_UART1_BASE 0xD4017000
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#define ARMD1_UART2_BASE 0xD4018000
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#define ARMD1_GPIO_BASE 0xD4019000
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#define ARMD1_SSP1_BASE 0xD401B000
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#define ARMD1_SSP2_BASE 0xD401C000
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#define ARMD1_MFPR_BASE 0xD401E000
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#define ARMD1_SSP3_BASE 0xD401F000
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#define ARMD1_SSP4_BASE 0xD4020000
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#define ARMD1_SSP5_BASE 0xD4021000
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#define ARMD1_UART3_BASE 0xD4026000
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#define ARMD1_MPMU_BASE 0xD4050000
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#define ARMD1_APMU_BASE 0xD4282800
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#define ARMD1_CPU_BASE 0xD4282C00
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/*
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* Main Power Management (MPMU) Registers
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* Refer Datasheet Appendix A.8
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*/
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struct armd1mpmu_registers {
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u8 pad0[0x08 - 0x00];
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u32 fccr; /*0x0008*/
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u32 pocr; /*0x000c*/
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u32 posr; /*0x0010*/
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u32 succr; /*0x0014*/
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u8 pad1[0x030 - 0x014 - 4];
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u32 gpcr; /*0x0030*/
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u8 pad2[0x200 - 0x030 - 4];
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u32 wdtpcr; /*0x0200*/
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u8 pad3[0x1000 - 0x200 - 4];
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u32 apcr; /*0x1000*/
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u32 apsr; /*0x1004*/
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u8 pad4[0x1020 - 0x1004 - 4];
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u32 aprr; /*0x1020*/
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u32 acgr; /*0x1024*/
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u32 arsr; /*0x1028*/
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};
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/*
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* Application Subsystem Power Management
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* Refer Datasheet Appendix A.9
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*/
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struct armd1apmu_registers {
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u32 pcr; /* 0x000 */
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u32 ccr; /* 0x004 */
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u32 pad1;
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u32 ccsr; /* 0x00C */
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u32 fc_timer; /* 0x010 */
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u32 pad2;
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u32 ideal_cfg; /* 0x018 */
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u8 pad3[0x04C - 0x018 - 4];
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u32 lcdcrc; /* 0x04C */
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u32 cciccrc; /* 0x050 */
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u32 sd1crc; /* 0x054 */
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u32 sd2crc; /* 0x058 */
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u32 usbcrc; /* 0x05C */
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u32 nfccrc; /* 0x060 */
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u32 dmacrc; /* 0x064 */
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u32 pad4;
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u32 buscrc; /* 0x06C */
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u8 pad5[0x07C - 0x06C - 4];
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u32 wake_clr; /* 0x07C */
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u8 pad6[0x090 - 0x07C - 4];
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u32 core_status; /* 0x090 */
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u32 rfsc; /* 0x094 */
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u32 imr; /* 0x098 */
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u32 irwc; /* 0x09C */
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u32 isr; /* 0x0A0 */
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u8 pad7[0x0B0 - 0x0A0 - 4];
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u32 mhst; /* 0x0B0 */
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u32 msr; /* 0x0B4 */
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u8 pad8[0x0C0 - 0x0B4 - 4];
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u32 msst; /* 0x0C0 */
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u32 pllss; /* 0x0C4 */
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u32 smb; /* 0x0C8 */
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u32 gccrc; /* 0x0CC */
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u8 pad9[0x0D4 - 0x0CC - 4];
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u32 smccrc; /* 0x0D4 */
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u32 pad10;
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u32 xdcrc; /* 0x0DC */
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u32 sd3crc; /* 0x0E0 */
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u32 sd4crc; /* 0x0E4 */
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u8 pad11[0x0F0 - 0x0E4 - 4];
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u32 cfcrc; /* 0x0F0 */
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u32 mspcrc; /* 0x0F4 */
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u32 cmucrc; /* 0x0F8 */
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u32 fecrc; /* 0x0FC */
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u32 pciecrc; /* 0x100 */
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u32 epdcrc; /* 0x104 */
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};
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/*
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* APB1 Clock Reset/Control Registers
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* Refer Datasheet Appendix A.10
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*/
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struct armd1apb1_registers {
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u32 uart1; /*0x000*/
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u32 uart2; /*0x004*/
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u32 gpio; /*0x008*/
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u32 pwm1; /*0x00c*/
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u32 pwm2; /*0x010*/
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u32 pwm3; /*0x014*/
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u32 pwm4; /*0x018*/
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u8 pad0[0x028 - 0x018 - 4];
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u32 rtc; /*0x028*/
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u32 twsi0; /*0x02c*/
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u32 kpc; /*0x030*/
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u32 timers; /*0x034*/
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u8 pad1[0x03c - 0x034 - 4];
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u32 aib; /*0x03c*/
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u32 sw_jtag; /*0x040*/
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u32 timer1; /*0x044*/
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u32 onewire; /*0x048*/
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u8 pad2[0x050 - 0x048 - 4];
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u32 asfar; /*0x050 AIB Secure First Access Reg*/
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u32 assar; /*0x054 AIB Secure Second Access Reg*/
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u8 pad3[0x06c - 0x054 - 4];
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u32 twsi1; /*0x06c*/
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u32 uart3; /*0x070*/
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u8 pad4[0x07c - 0x070 - 4];
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u32 timer2; /*0x07C*/
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u8 pad5[0x084 - 0x07c - 4];
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u32 ac97; /*0x084*/
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};
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#endif /* CONFIG_ARMADA100 */
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#endif /* _ASM_ARCH_ARMADA100_H */
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