upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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461 lines
11 KiB
461 lines
11 KiB
/*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on da830evm.c. Original Copyrights follow:
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*
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emif_defs.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/io.h>
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#include <asm/arch/davinci_misc.h>
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#include <hwconfig.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
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/* SPI0 pin muxer settings */
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static const struct pinmux_config spi1_pins[] = {
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{ pinmux(5), 1, 1 },
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{ pinmux(5), 1, 2 },
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{ pinmux(5), 1, 4 },
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{ pinmux(5), 1, 5 }
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};
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/* UART pin muxer settings */
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static const struct pinmux_config uart_pins[] = {
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{ pinmux(0), 4, 6 },
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{ pinmux(0), 4, 7 },
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{ pinmux(4), 2, 4 },
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{ pinmux(4), 2, 5 }
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};
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#ifdef CONFIG_DRIVER_TI_EMAC
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static const struct pinmux_config emac_pins[] = {
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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{ pinmux(14), 8, 2 },
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{ pinmux(14), 8, 3 },
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{ pinmux(14), 8, 4 },
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{ pinmux(14), 8, 5 },
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{ pinmux(14), 8, 6 },
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{ pinmux(14), 8, 7 },
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{ pinmux(15), 8, 1 },
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#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
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{ pinmux(2), 8, 1 },
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{ pinmux(2), 8, 2 },
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{ pinmux(2), 8, 3 },
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{ pinmux(2), 8, 4 },
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{ pinmux(2), 8, 5 },
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{ pinmux(2), 8, 6 },
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{ pinmux(2), 8, 7 },
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{ pinmux(3), 8, 0 },
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{ pinmux(3), 8, 1 },
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{ pinmux(3), 8, 2 },
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{ pinmux(3), 8, 3 },
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{ pinmux(3), 8, 4 },
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{ pinmux(3), 8, 5 },
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{ pinmux(3), 8, 6 },
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{ pinmux(3), 8, 7 },
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#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
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{ pinmux(4), 8, 0 },
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{ pinmux(4), 8, 1 }
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};
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/* I2C pin muxer settings */
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static const struct pinmux_config i2c_pins[] = {
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{ pinmux(4), 2, 2 },
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{ pinmux(4), 2, 3 }
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};
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#ifdef CONFIG_NAND_DAVINCI
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const struct pinmux_config nand_pins[] = {
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{ pinmux(7), 1, 1 },
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{ pinmux(7), 1, 2 },
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{ pinmux(7), 1, 4 },
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{ pinmux(7), 1, 5 },
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{ pinmux(9), 1, 0 },
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{ pinmux(9), 1, 1 },
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{ pinmux(9), 1, 2 },
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{ pinmux(9), 1, 3 },
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{ pinmux(9), 1, 4 },
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{ pinmux(9), 1, 5 },
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{ pinmux(9), 1, 6 },
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{ pinmux(9), 1, 7 },
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{ pinmux(12), 1, 5 },
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{ pinmux(12), 1, 6 }
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};
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#elif defined(CONFIG_USE_NOR)
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/* NOR pin muxer settings */
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const struct pinmux_config nor_pins[] = {
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/* GP0[11] is required for NOR to work on Rev 3 EVMs */
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{ pinmux(0), 8, 4 }, /* GP0[11] */
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{ pinmux(5), 1, 6 },
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{ pinmux(6), 1, 6 },
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{ pinmux(7), 1, 0 },
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{ pinmux(7), 1, 4 },
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{ pinmux(7), 1, 5 },
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{ pinmux(8), 1, 0 },
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{ pinmux(8), 1, 1 },
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{ pinmux(8), 1, 2 },
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{ pinmux(8), 1, 3 },
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{ pinmux(8), 1, 4 },
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{ pinmux(8), 1, 5 },
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{ pinmux(8), 1, 6 },
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{ pinmux(8), 1, 7 },
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{ pinmux(9), 1, 0 },
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{ pinmux(9), 1, 1 },
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{ pinmux(9), 1, 2 },
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{ pinmux(9), 1, 3 },
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{ pinmux(9), 1, 4 },
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{ pinmux(9), 1, 5 },
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{ pinmux(9), 1, 6 },
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{ pinmux(9), 1, 7 },
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{ pinmux(10), 1, 0 },
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{ pinmux(10), 1, 1 },
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{ pinmux(10), 1, 2 },
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{ pinmux(10), 1, 3 },
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{ pinmux(10), 1, 4 },
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{ pinmux(10), 1, 5 },
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{ pinmux(10), 1, 6 },
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{ pinmux(10), 1, 7 },
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{ pinmux(11), 1, 0 },
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{ pinmux(11), 1, 1 },
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{ pinmux(11), 1, 2 },
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{ pinmux(11), 1, 3 },
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{ pinmux(11), 1, 4 },
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{ pinmux(11), 1, 5 },
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{ pinmux(11), 1, 6 },
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{ pinmux(11), 1, 7 },
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{ pinmux(12), 1, 0 },
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{ pinmux(12), 1, 1 },
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{ pinmux(12), 1, 2 },
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{ pinmux(12), 1, 3 },
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{ pinmux(12), 1, 4 },
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{ pinmux(12), 1, 5 },
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{ pinmux(12), 1, 6 },
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{ pinmux(12), 1, 7 }
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};
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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#define HAS_RMII 1
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#else
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#define HAS_RMII 0
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#endif
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#endif /* CONFIG_DRIVER_TI_EMAC */
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void dsp_lpsc_on(unsigned domain, unsigned int id)
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{
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dv_reg_p mdstat, mdctl, ptstat, ptcmd;
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struct davinci_psc_regs *psc_regs;
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psc_regs = davinci_psc0_regs;
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mdstat = &psc_regs->psc0.mdstat[id];
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mdctl = &psc_regs->psc0.mdctl[id];
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ptstat = &psc_regs->ptstat;
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ptcmd = &psc_regs->ptcmd;
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while (*ptstat & (0x1 << domain))
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;
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if ((*mdstat & 0x1f) == 0x03)
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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*ptcmd = 0x1 << domain;
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while (*ptstat & (0x1 << domain))
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;
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while ((*mdstat & 0x1f) != 0x03)
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; /* Probably an overkill... */
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}
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static void dspwake(void)
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{
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unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
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u32 val;
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/* if the device is ARM only, return */
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if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
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return;
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if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
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return;
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*resetvect++ = 0x1E000; /* DSP Idle */
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/* clear out the next 10 words as NOP */
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memset(resetvect, 0, sizeof(unsigned) *10);
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/* setup the DSP reset vector */
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writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
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dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
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val = readl(PSC0_MDCTL + (15 * 4));
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val |= 0x100;
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writel(val, (PSC0_MDCTL + (15 * 4)));
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}
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int misc_init_r(void)
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{
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dspwake();
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return 0;
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}
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static const struct pinmux_resource pinmuxes[] = {
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#ifdef CONFIG_SPI_FLASH
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PINMUX_ITEM(spi1_pins),
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#endif
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PINMUX_ITEM(uart_pins),
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PINMUX_ITEM(i2c_pins),
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#ifdef CONFIG_NAND_DAVINCI
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PINMUX_ITEM(nand_pins),
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#elif defined(CONFIG_USE_NOR)
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PINMUX_ITEM(nor_pins),
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#endif
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};
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static const struct lpsc_resource lpsc[] = {
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
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{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
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{ DAVINCI_LPSC_EMAC }, /* image download */
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{ DAVINCI_LPSC_UART2 }, /* console */
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{ DAVINCI_LPSC_GPIO },
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};
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#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
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#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
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#endif
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/*
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* get_board_rev() - setup to pass kernel board revision information
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* Returns:
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* bit[0-3] Maximum cpu clock rate supported by onboard SoC
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* 0000b - 300 MHz
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* 0001b - 372 MHz
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* 0010b - 408 MHz
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* 0011b - 456 MHz
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*/
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u32 get_board_rev(void)
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{
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char *s;
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u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
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u32 rev = 0;
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s = getenv("maxcpuclk");
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if (s)
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maxcpuclk = simple_strtoul(s, NULL, 10);
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if (maxcpuclk >= 456000000)
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rev = 3;
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else if (maxcpuclk >= 408000000)
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rev = 2;
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else if (maxcpuclk >= 372000000)
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rev = 1;
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return rev;
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}
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int board_init(void)
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{
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#ifdef CONFIG_USE_NOR
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u32 val;
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#endif
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#ifndef CONFIG_USE_IRQ
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irq_init();
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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/*
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* NAND CS setup - cycle counts based on da850evm NAND timings in the
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* Linux kernel @ 25MHz EMIFA
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*/
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writel((DAVINCI_ABCR_WSETUP(0) |
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DAVINCI_ABCR_WSTROBE(1) |
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DAVINCI_ABCR_WHOLD(0) |
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DAVINCI_ABCR_RSETUP(0) |
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DAVINCI_ABCR_RSTROBE(1) |
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DAVINCI_ABCR_RHOLD(0) |
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DAVINCI_ABCR_TA(1) |
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DAVINCI_ABCR_ASIZE_8BIT),
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&davinci_emif_regs->ab2cr); /* CS3 */
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#endif
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/*
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* Power on required peripherals
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* ARM does not have access by default to PSC0 and PSC1
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* assuming here that the DSP bootloader has set the IOPU
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* such that PSC access is available to ARM
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*/
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if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
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return 1;
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/* setup the SUSPSRC for ARM to control emulation suspend */
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writel(readl(&davinci_syscfg_regs->suspsrc) &
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~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
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DAVINCI_SYSCFG_SUSPSRC_UART2),
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&davinci_syscfg_regs->suspsrc);
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/* configure pinmux settings */
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if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
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return 1;
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#ifdef CONFIG_USE_NOR
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/* Set the GPIO direction as output */
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clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
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/* Set the output as low */
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val = readl(GPIO_BANK0_REG_SET_ADDR);
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val |= (0x01 << 11);
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writel(val, GPIO_BANK0_REG_CLR_ADDR);
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
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return 1;
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davinci_emac_mii_mode_sel(HAS_RMII);
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#endif /* CONFIG_DRIVER_TI_EMAC */
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/* enable the console UART */
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
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DAVINCI_UART_PWREMU_MGMT_UTRST),
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&davinci_uart2_ctrl_regs->pwremu_mgmt);
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_EMAC
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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/**
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* rmii_hw_init
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*
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* DA850/OMAP-L138 EVM can interface to a daughter card for
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* additional features. This card has an I2C GPIO Expander TCA6416
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* to select the required functions like camera, RMII Ethernet,
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* character LCD, video.
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*
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* Initialization of the expander involves configuring the
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* polarity and direction of the ports. P07-P05 are used here.
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* These ports are connected to a Mux chip which enables only one
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* functionality at a time.
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*
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* For RMII phy to respond, the MII MDIO clock has to be disabled
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* since both the PHY devices have address as zero. The MII MDIO
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* clock is controlled via GPIO2[6].
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*
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* This code is valid for Beta version of the hardware
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*/
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int rmii_hw_init(void)
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{
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const struct pinmux_config gpio_pins[] = {
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{ pinmux(6), 8, 1 }
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};
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u_int8_t buf[2];
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unsigned int temp;
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int ret;
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/* PinMux for GPIO */
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if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
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return 1;
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/* I2C Exapnder configuration */
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/* Set polarity to non-inverted */
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buf[0] = 0x0;
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buf[1] = 0x0;
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ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
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if (ret) {
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printf("\nExpander @ 0x%02x write FAILED!!!\n",
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CONFIG_SYS_I2C_EXPANDER_ADDR);
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return ret;
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}
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/* Configure P07-P05 as outputs */
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buf[0] = 0x1f;
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buf[1] = 0xff;
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ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
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if (ret) {
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printf("\nExpander @ 0x%02x write FAILED!!!\n",
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CONFIG_SYS_I2C_EXPANDER_ADDR);
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}
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/* For Ethernet RMII selection
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* P07(SelA)=0
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* P06(SelB)=1
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* P05(SelC)=1
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*/
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if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
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printf("\nExpander @ 0x%02x read FAILED!!!\n",
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CONFIG_SYS_I2C_EXPANDER_ADDR);
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}
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buf[0] &= 0x1f;
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buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
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if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
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printf("\nExpander @ 0x%02x write FAILED!!!\n",
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CONFIG_SYS_I2C_EXPANDER_ADDR);
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}
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/* Set the output as high */
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temp = REG(GPIO_BANK2_REG_SET_ADDR);
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temp |= (0x01 << 6);
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REG(GPIO_BANK2_REG_SET_ADDR) = temp;
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/* Set the GPIO direction as output */
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temp = REG(GPIO_BANK2_REG_DIR_ADDR);
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temp &= ~(0x01 << 6);
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REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
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return 0;
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}
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#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
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/*
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* Initializes on-board ethernet controllers.
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*/
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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/* Select RMII fucntion through the expander */
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if (rmii_hw_init())
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printf("RMII hardware init failed!!!\n");
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#endif
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if (!davinci_emac_initialize()) {
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printf("Error: Ethernet init failed!\n");
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return -1;
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}
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return 0;
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}
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#endif /* CONFIG_DRIVER_TI_EMAC */
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