upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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147 lines
3.6 KiB
147 lines
3.6 KiB
/*
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* Copyright (C) 2013,2014 Renesas Electronics Corporation
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* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __EHCI_RMOBILE_H__
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#define __EHCI_RMOBILE_H__
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/* Register offset */
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#define OHCI_OFFSET 0x00
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#define OHCI_SIZE 0x1000
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#define EHCI_OFFSET 0x1000
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#define EHCI_SIZE 0x1000
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#define EHCI_USBCMD (EHCI_OFFSET + 0x0020)
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/* USBCTR */
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#define DIRPD (1 << 8)
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#define PLL_RST (1 << 2)
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#define PCICLK_MASK (1 << 1)
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#define USBH_RST (1 << 0)
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/* CMND_STS */
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#define SERREN (1 << 8)
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#define PERREN (1 << 6)
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#define MASTEREN (1 << 2)
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#define MEMEN (1 << 1)
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/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
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#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0))
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/* AHBPCI_WIN1_CTR */
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#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1))
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#define AHB_CFG_AHBPCI 0x40000000
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#define AHB_CFG_HOST 0x80000000
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/* AHBPCI_WIN2_CTR */
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#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1))
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/* PCI_INT_ENABLE */
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#define USBH_PMEEN (1 << 19)
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#define USBH_INTBEN (1 << 17)
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#define USBH_INTAEN (1 << 16)
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/* AHB_BUS_CTR */
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#define SMODE_READY_CTR (1 << 17)
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#define SMODE_READ_BURST (1 << 16)
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#define MMODE_HBUSREQ (1 << 7)
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#define MMODE_BOUNDARY ((1 << 6)|(1 << 5))
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#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3))
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#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3))
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#define MMODE_WR_INCR (1 << 2)
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#define MMODE_BYTE_BURST (1 << 1)
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#define MMODE_HTRANS (1 << 0)
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/* PCI_ARBITER_CTR */
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#define PCIBUS_PARK_TIMER 0x00FF0000
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#define PCIBUS_PARK_TIMER_SET 0x00070000
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#define PCIBP_MODE (1 << 12)
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#define PCIREQ7 (1 << 7)
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#define PCIREQ6 (1 << 6)
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#define PCIREQ5 (1 << 5)
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#define PCIREQ4 (1 << 4)
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#define PCIREQ3 (1 << 3)
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#define PCIREQ2 (1 << 2)
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#define PCIREQ1 (1 << 1)
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#define PCIREQ0 (1 << 0)
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#define SMSTPCR7 0xE615014C
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#define SMSTPCR703 (1 << 3)
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/* Init AHB master and slave functions of the host logic */
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#define AHB_BUS_CTR_INIT \
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(SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
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MMODE_BYTE_BURST | MMODE_HTRANS)
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#define USBCTR_WIN_SIZE_1GB 0x800
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/* PCI Configuration Registers */
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#define PCI_CONF_OHCI_OFFSET 0x10000
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#define PCI_CONF_EHCI_OFFSET 0x10100
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struct ahb_pciconf {
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u32 vid_did;
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u32 cmnd_sts;
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u32 rev;
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u32 cache_line;
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u32 basead;
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};
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/* PCI Configuration Registers for AHB-PCI Bridge Registers */
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#define PCI_CONF_AHBPCI_OFFSET 0x10000
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struct ahbconf_pci_bridge {
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u32 vid_did; /* 0x00 */
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u32 cmnd_sts;
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u32 revid_cc;
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u32 cls_lt_ht_bist;
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u32 basead; /* 0x10 */
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u32 win1_basead;
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u32 win2_basead;
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u32 dummy0[5];
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u32 ssvdi_ssid; /* 0x2C */
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u32 dummy1[4];
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u32 intr_line_pin;
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};
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/* AHB-PCI Bridge PCI Communication Registers */
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#define AHBPCI_OFFSET 0x10800
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struct ahbcom_pci_bridge {
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u32 pciahb_win1_ctr; /* 0x00 */
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u32 pciahb_win2_ctr;
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u32 pciahb_dct_ctr;
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u32 dummy0;
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u32 ahbpci_win1_ctr; /* 0x10 */
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u32 ahbpci_win2_ctr;
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u32 dummy1;
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u32 ahbpci_dct_ctr;
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u32 pci_int_enable; /* 0x20 */
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u32 pci_int_status;
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u32 dummy2[2];
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u32 ahb_bus_ctr; /* 0x30 */
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u32 usbctr;
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u32 dummy3[2];
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u32 pci_arbiter_ctr; /* 0x40 */
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u32 dummy4;
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u32 pci_unit_rev; /* 0x48 */
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};
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struct rmobile_ehci_reg {
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u32 hciversion; /* hciversion/caplength */
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u32 hcsparams; /* hcsparams */
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u32 hccparams; /* hccparams */
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u32 hcsp_portroute; /* hcsp_portroute */
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u32 usbcmd; /* usbcmd */
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u32 usbsts; /* usbsts */
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u32 usbintr; /* usbintr */
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u32 frindex; /* frindex */
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u32 ctrldssegment; /* ctrldssegment */
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u32 periodiclistbase; /* periodiclistbase */
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u32 asynclistaddr; /* asynclistaddr */
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u32 dummy[9];
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u32 configflag; /* configflag */
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u32 portsc; /* portsc */
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};
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#endif /* __EHCI_RMOBILE_H__ */
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