upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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157 lines
5.2 KiB
157 lines
5.2 KiB
/*
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* include/asm-armnommu/arch-netarm/netarm_mem_module.h
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*
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* Copyright (C) 2000, 2001 NETsilicon, Inc.
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* Copyright (C) 2000, 2001 Red Hat, Inc.
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*
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* This software is copyrighted by Red Hat. LICENSEE agrees that
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* it will not delete this copyright notice, trademarks or protective
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* notices from any copy made by LICENSEE.
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*
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* This software is provided "AS-IS" and any express or implied
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* warranties or conditions, including but not limited to any
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* implied warranties of merchantability and fitness for a particular
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* purpose regarding this software. In no event shall Red Hat
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* be liable for any indirect, consequential, or incidental damages,
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* loss of profits or revenue, loss of use or data, or interruption
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* of business, whether the alleged damages are labeled in contract,
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* tort, or indemnity.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* author(s) : Joe deBlaquiere
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*/
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#ifndef __NETARM_MEM_MODULE_REGISTERS_H
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#define __NETARM_MEM_MODULE_REGISTERS_H
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/* GEN unit register offsets */
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#define NETARM_MEM_MODULE_BASE (0xFFC00000)
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#define NETARM_MEM_MODULE_CONFIG (0x00)
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#define NETARM_MEM_CS0_BASE_ADDR (0x10)
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#define NETARM_MEM_CS0_OPTIONS (0x14)
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#define NETARM_MEM_CS1_BASE_ADDR (0x20)
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#define NETARM_MEM_CS1_OPTIONS (0x24)
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#define NETARM_MEM_CS2_BASE_ADDR (0x30)
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#define NETARM_MEM_CS2_OPTIONS (0x34)
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#define NETARM_MEM_CS3_BASE_ADDR (0x40)
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#define NETARM_MEM_CS3_OPTIONS (0x44)
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#define NETARM_MEM_CS4_BASE_ADDR (0x50)
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#define NETARM_MEM_CS4_OPTIONS (0x54)
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/* select bitfield defintions */
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/* Module Configuration Register ( 0xFFC0_0000 ) */
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#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000)
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#define NETARM_MEM_CFG_REFRESH_EN (0x00800000)
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#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000)
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#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000)
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#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000)
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#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000)
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#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000)
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#define NETARM_MEM_CFG_A27_ADDR (0x00080000)
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#define NETARM_MEM_CFG_A27_CS0OE (0x00000000)
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#define NETARM_MEM_CFG_A26_ADDR (0x00040000)
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#define NETARM_MEM_CFG_A26_CS0WE (0x00000000)
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#define NETARM_MEM_CFG_A25_ADDR (0x00020000)
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#define NETARM_MEM_CFG_A25_BLAST (0x00000000)
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#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000)
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/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
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/* the expression will round down, so make sure to reverse it to verify */
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/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */
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/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
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#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
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(((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
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) - (1) ) << (24)))
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#if 0
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/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
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/* the expression will round down, so make sure to reverse it toverify */
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/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */
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#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
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(((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
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) - (1) ) << (24)))
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#endif
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/* Base Address Registers (0xFFC0_00X0) */
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#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000)
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/* macro to define base */
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#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
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#define NETARM_MEM_BAR_DRAM_FP (0x00000000)
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#define NETARM_MEM_BAR_DRAM_EDO (0x00000100)
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#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200)
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#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000)
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#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080)
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#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000)
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#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020)
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#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010)
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#define NETARM_MEM_BAR_DRAM_SEL (0x00000008)
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#define NETARM_MEM_BAR_BURST_EN (0x00000004)
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#define NETARM_MEM_BAR_WRT_PROT (0x00000002)
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#define NETARM_MEM_BAR_VALID (0x00000001)
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/* Option Registers (0xFFC0_00X4) */
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/* macro to define which bits of the base are significant */
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#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
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#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00)
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#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
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#define NETARM_MEM_OPT_BCYC_1 (0x00000000)
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#define NETARM_MEM_OPT_BCYC_2 (0x00000040)
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#define NETARM_MEM_OPT_BCYC_3 (0x00000080)
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#define NETARM_MEM_OPT_BCYC_4 (0x000000C0)
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#define NETARM_MEM_OPT_BSIZE_2 (0x00000000)
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#define NETARM_MEM_OPT_BSIZE_4 (0x00000010)
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#define NETARM_MEM_OPT_BSIZE_8 (0x00000020)
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#define NETARM_MEM_OPT_BSIZE_16 (0x00000030)
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#define NETARM_MEM_OPT_32BIT (0x00000000)
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#define NETARM_MEM_OPT_16BIT (0x00000004)
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#define NETARM_MEM_OPT_8BIT (0x00000008)
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#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C)
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#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C)
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#define NETARM_MEM_OPT_READ_ASYNC (0x00000000)
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#define NETARM_MEM_OPT_READ_SYNC (0x00000002)
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#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
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#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
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#endif
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