upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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356 lines
8.5 KiB
356 lines
8.5 KiB
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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#include "xor_regs.h"
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/* defines */
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#ifdef MV_DEBUG
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#define DB(x) x
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#else
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#define DB(x)
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#endif
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static u32 ui_xor_regs_ctrl_backup;
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static u32 ui_xor_regs_base_backup[MAX_CS];
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static u32 ui_xor_regs_mask_backup[MAX_CS];
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void mv_sys_xor_init(u32 num_of_cs, u32 cs_ena, u32 cs_size, u32 base_delta)
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{
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u32 reg, ui, base, cs_count;
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ui_xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0));
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for (ui = 0; ui < MAX_CS; ui++)
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ui_xor_regs_base_backup[ui] =
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reg_read(XOR_BASE_ADDR_REG(0, ui));
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for (ui = 0; ui < MAX_CS; ui++)
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ui_xor_regs_mask_backup[ui] =
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reg_read(XOR_SIZE_MASK_REG(0, ui));
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reg = 0;
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for (ui = 0; ui < (num_of_cs); ui++) {
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/* Enable Window x for each CS */
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reg |= (0x1 << (ui));
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/* Enable Window x for each CS */
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reg |= (0x3 << ((ui * 2) + 16));
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}
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reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg);
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cs_count = 0;
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for (ui = 0; ui < num_of_cs; ui++) {
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if (cs_ena & (1 << ui)) {
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/*
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* window x - Base - 0x00000000,
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* Attribute 0x0e - DRAM
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*/
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base = cs_size * ui + base_delta;
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switch (ui) {
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case 0:
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base |= 0xe00;
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break;
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case 1:
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base |= 0xd00;
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break;
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case 2:
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base |= 0xb00;
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break;
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case 3:
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base |= 0x700;
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break;
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}
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reg_write(XOR_BASE_ADDR_REG(0, cs_count), base);
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/* window x - Size */
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reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x7fff0000);
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cs_count++;
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}
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}
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mv_xor_hal_init(1);
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return;
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}
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void mv_sys_xor_finish(void)
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{
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u32 ui;
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reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup);
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for (ui = 0; ui < MAX_CS; ui++)
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reg_write(XOR_BASE_ADDR_REG(0, ui),
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ui_xor_regs_base_backup[ui]);
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for (ui = 0; ui < MAX_CS; ui++)
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reg_write(XOR_SIZE_MASK_REG(0, ui),
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ui_xor_regs_mask_backup[ui]);
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reg_write(XOR_ADDR_OVRD_REG(0, 0), 0);
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}
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/*
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* mv_xor_hal_init - Initialize XOR engine
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*
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* DESCRIPTION:
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* This function initialize XOR unit.
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
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*/
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void mv_xor_hal_init(u32 xor_chan_num)
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{
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u32 i;
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/* Abort any XOR activity & set default configuration */
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for (i = 0; i < xor_chan_num; i++) {
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mv_xor_command_set(i, MV_STOP);
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mv_xor_ctrl_set(i, (1 << XEXCR_REG_ACC_PROTECT_OFFS) |
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(4 << XEXCR_DST_BURST_LIMIT_OFFS) |
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(4 << XEXCR_SRC_BURST_LIMIT_OFFS));
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}
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}
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/*
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* mv_xor_ctrl_set - Set XOR channel control registers
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*
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* DESCRIPTION:
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*
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* INPUT:
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
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* NOTE:
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* This function does not modify the Operation_mode field of control register.
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*/
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int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
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{
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u32 old_value;
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/* update the XOR Engine [0..1] Configuration Registers (XEx_c_r) */
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old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) &
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XEXCR_OPERATION_MODE_MASK;
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xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
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xor_ctrl |= old_value;
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reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
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return MV_OK;
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}
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int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size,
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u32 init_val_high, u32 init_val_low)
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{
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u32 temp;
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/* Parameter checking */
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if (chan >= MV_XOR_MAX_CHAN)
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return MV_BAD_PARAM;
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if (MV_ACTIVE == mv_xor_state_get(chan))
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return MV_BUSY;
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if ((block_size < XEXBSR_BLOCK_SIZE_MIN_VALUE) ||
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(block_size > XEXBSR_BLOCK_SIZE_MAX_VALUE))
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return MV_BAD_PARAM;
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/* set the operation mode to Memory Init */
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temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
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temp &= ~XEXCR_OPERATION_MODE_MASK;
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temp |= XEXCR_OPERATION_MODE_MEM_INIT;
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reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp);
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/*
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* update the start_ptr field in XOR Engine [0..1] Destination Pointer
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* Register
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*/
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reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr);
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/*
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* update the Block_size field in the XOR Engine[0..1] Block Size
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* Registers
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*/
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reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
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block_size);
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/*
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* update the field Init_val_l in the XOR Engine Initial Value Register
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* Low (XEIVRL)
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*/
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reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low);
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/*
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* update the field Init_val_h in the XOR Engine Initial Value Register
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* High (XEIVRH)
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*/
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reg_write(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), init_val_high);
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/* start transfer */
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reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
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XEXACTR_XESTART_MASK);
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return MV_OK;
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}
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/*
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* mv_xor_state_get - Get XOR channel state.
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*
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* DESCRIPTION:
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* XOR channel activity state can be active, idle, paused.
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* This function retrunes the channel activity state.
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*
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* INPUT:
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* chan - the channel number
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* XOR_CHANNEL_IDLE - If the engine is idle.
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* XOR_CHANNEL_ACTIVE - If the engine is busy.
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* XOR_CHANNEL_PAUSED - If the engine is paused.
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* MV_UNDEFINED_STATE - If the engine state is undefind or there is no
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* such engine
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*/
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enum mv_state mv_xor_state_get(u32 chan)
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{
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u32 state;
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/* Parameter checking */
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if (chan >= MV_XOR_MAX_CHAN) {
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DB(printf("%s: ERR. Invalid chan num %d\n", __func__, chan));
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return MV_UNDEFINED_STATE;
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}
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/* read the current state */
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state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
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state &= XEXACTR_XESTATUS_MASK;
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/* return the state */
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switch (state) {
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case XEXACTR_XESTATUS_IDLE:
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return MV_IDLE;
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case XEXACTR_XESTATUS_ACTIVE:
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return MV_ACTIVE;
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case XEXACTR_XESTATUS_PAUSED:
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return MV_PAUSED;
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}
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return MV_UNDEFINED_STATE;
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}
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/*
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* mv_xor_command_set - Set command of XOR channel
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*
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* DESCRIPTION:
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* XOR channel can be started, idle, paused and restarted.
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* Paused can be set only if channel is active.
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* Start can be set only if channel is idle or paused.
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* Restart can be set only if channel is paused.
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* Stop can be set only if channel is active.
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*
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* INPUT:
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* chan - The channel number
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* command - The command type (start, stop, restart, pause)
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_OK on success , MV_BAD_PARAM on erroneous parameter, MV_ERROR on
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* undefind XOR engine mode
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*/
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int mv_xor_command_set(u32 chan, enum mv_command command)
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{
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enum mv_state state;
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/* Parameter checking */
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if (chan >= MV_XOR_MAX_CHAN) {
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DB(printf("%s: ERR. Invalid chan num %d\n", __func__, chan));
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return MV_BAD_PARAM;
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}
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/* get the current state */
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state = mv_xor_state_get(chan);
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if ((command == MV_START) && (state == MV_IDLE)) {
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/* command is start and current state is idle */
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reg_bit_set(XOR_ACTIVATION_REG
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(XOR_UNIT(chan), XOR_CHAN(chan)),
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XEXACTR_XESTART_MASK);
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return MV_OK;
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} else if ((command == MV_STOP) && (state == MV_ACTIVE)) {
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/* command is stop and current state is active */
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reg_bit_set(XOR_ACTIVATION_REG
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(XOR_UNIT(chan), XOR_CHAN(chan)),
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XEXACTR_XESTOP_MASK);
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return MV_OK;
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} else if (((enum mv_state)command == MV_PAUSED) &&
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(state == MV_ACTIVE)) {
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/* command is paused and current state is active */
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reg_bit_set(XOR_ACTIVATION_REG
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(XOR_UNIT(chan), XOR_CHAN(chan)),
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XEXACTR_XEPAUSE_MASK);
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return MV_OK;
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} else if ((command == MV_RESTART) && (state == MV_PAUSED)) {
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/* command is restart and current state is paused */
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reg_bit_set(XOR_ACTIVATION_REG
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(XOR_UNIT(chan), XOR_CHAN(chan)),
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XEXACTR_XERESTART_MASK);
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return MV_OK;
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} else if ((command == MV_STOP) && (state == MV_IDLE)) {
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/* command is stop and current state is active */
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return MV_OK;
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}
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/* illegal command */
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DB(printf("%s: ERR. Illegal command\n", __func__));
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return MV_BAD_PARAM;
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}
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void ddr3_new_tip_ecc_scrub(void)
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{
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u32 cs_c, max_cs;
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u32 cs_ena = 0;
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printf("DDR3 Training Sequence - Start scrubbing\n");
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max_cs = hws_ddr3_tip_max_cs_get();
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for (cs_c = 0; cs_c < max_cs; cs_c++)
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cs_ena |= 1 << cs_c;
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mv_sys_xor_init(max_cs, cs_ena, 0x80000000, 0);
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mv_xor_mem_init(0, 0x00000000, 0x80000000, 0xdeadbeef, 0xdeadbeef);
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/* wait for previous transfer completion */
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while (mv_xor_state_get(0) != MV_IDLE)
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;
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mv_xor_mem_init(0, 0x80000000, 0x40000000, 0xdeadbeef, 0xdeadbeef);
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/* wait for previous transfer completion */
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while (mv_xor_state_get(0) != MV_IDLE)
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;
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/* Return XOR State */
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mv_sys_xor_finish();
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printf("DDR3 Training Sequence - End scrubbing\n");
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}
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