upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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351 lines
8.2 KiB
351 lines
8.2 KiB
/*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pinmux.h>
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#else
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#include <asm/arch/s3c24x0_cpu.h>
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#endif
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#include <asm/io.h>
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#include <i2c.h>
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#include "s3c24x0_i2c.h"
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#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
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#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
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#else
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#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Wait til the byte transfer is completed.
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*
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* @param i2c- pointer to the appropriate i2c register bank.
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* @return I2C_OK, if transmission was ACKED
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* I2C_NACK, if transmission was NACKED
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* I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
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*/
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static int WaitForXfer(struct s3c24x0_i2c *i2c)
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{
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ulong start_time = get_timer(0);
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do {
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if (readl(&i2c->iiccon) & I2CCON_IRPND)
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return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
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I2C_NACK : I2C_OK;
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} while (get_timer(start_time) < I2C_TIMEOUT_MS);
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return I2C_NOK_TOUT;
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}
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static void read_write_byte(struct s3c24x0_i2c *i2c)
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{
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clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
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}
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static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
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{
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ulong freq, pres = 16, div;
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#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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freq = get_i2c_clk();
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#else
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freq = get_PCLK();
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#endif
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/* calculate prescaler and divisor values */
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if ((freq / pres / (16 + 1)) > speed)
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/* set prescaler to 512 */
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pres = 512;
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div = 0;
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while ((freq / pres / (div + 1)) > speed)
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div++;
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/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
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writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
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/* init to SLAVE REVEIVE and set slaveaddr */
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writel(0, &i2c->iicstat);
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writel(slaveadd, &i2c->iicadd);
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/* program Master Transmit (and implicit STOP) */
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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}
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static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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{
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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i2c_bus->clock_frequency = speed;
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i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
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SYS_I2C_S3C24X0_SLAVE_ADDR);
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return 0;
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}
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/*
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* cmd_type is 0 for write, 1 for read.
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*
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* addr_len can take any value from 0-255, it is only limited
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* by the char, we could make it larger if needed. If it is
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* 0 we skip the address write cycle.
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*/
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static int i2c_transfer(struct s3c24x0_i2c *i2c,
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unsigned char cmd_type,
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unsigned char chip,
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unsigned char addr[],
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unsigned char addr_len,
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unsigned char data[],
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unsigned short data_len)
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{
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int i = 0, result;
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ulong start_time = get_timer(0);
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if (data == 0 || data_len == 0) {
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/*Don't support data transfer of no length or to address 0 */
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debug("i2c_transfer: bad call\n");
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return I2C_NOK;
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}
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while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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if (get_timer(start_time) > I2C_TIMEOUT_MS)
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return I2C_NOK_TOUT;
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}
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writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
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/* Get the slave chip address going */
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writel(chip, &i2c->iicds);
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if ((cmd_type == I2C_WRITE) || (addr && addr_len))
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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else
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writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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/* Wait for chip address to transmit. */
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result = WaitForXfer(i2c);
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if (result != I2C_OK)
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goto bailout;
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/* If register address needs to be transmitted - do it now. */
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if (addr && addr_len) {
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while ((i < addr_len) && (result == I2C_OK)) {
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writel(addr[i++], &i2c->iicds);
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read_write_byte(i2c);
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result = WaitForXfer(i2c);
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}
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i = 0;
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if (result != I2C_OK)
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goto bailout;
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}
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switch (cmd_type) {
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case I2C_WRITE:
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while ((i < data_len) && (result == I2C_OK)) {
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writel(data[i++], &i2c->iicds);
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read_write_byte(i2c);
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result = WaitForXfer(i2c);
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}
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break;
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case I2C_READ:
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if (addr && addr_len) {
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/*
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* Register address has been sent, now send slave chip
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* address again to start the actual read transaction.
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*/
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writel(chip, &i2c->iicds);
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/* Generate a re-START. */
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writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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read_write_byte(i2c);
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result = WaitForXfer(i2c);
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if (result != I2C_OK)
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goto bailout;
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}
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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writel(readl(&i2c->iiccon)
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& ~I2CCON_ACKGEN,
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&i2c->iiccon);
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read_write_byte(i2c);
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result = WaitForXfer(i2c);
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data[i++] = readl(&i2c->iicds);
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}
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if (result == I2C_NACK)
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result = I2C_OK; /* Normal terminated read. */
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break;
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default:
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debug("i2c_transfer: bad call\n");
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result = I2C_NOK;
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break;
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}
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bailout:
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/* Send STOP. */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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read_write_byte(i2c);
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return result;
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}
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static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
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{
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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uchar buf[1];
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int ret;
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buf[0] = 0;
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/*
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* What is needed is to send the chip address and verify that the
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* address was <ACK>ed (i.e. there was a chip at that address which
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* drove the data line low).
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*/
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ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
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return ret != I2C_OK;
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}
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static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
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int seq)
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{
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struct s3c24x0_i2c *i2c = i2c_bus->regs;
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bool is_read = msg->flags & I2C_M_RD;
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uint status;
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uint addr;
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int ret, i;
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if (!seq)
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setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
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/* Get the slave chip address going */
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addr = msg->addr << 1;
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writel(addr, &i2c->iicds);
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status = I2C_TXRX_ENA | I2C_START_STOP;
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if (is_read)
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status |= I2C_MODE_MR;
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else
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status |= I2C_MODE_MT;
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writel(status, &i2c->iicstat);
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if (seq)
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read_write_byte(i2c);
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/* Wait for chip address to transmit */
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ret = WaitForXfer(i2c);
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if (ret)
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goto err;
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if (is_read) {
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for (i = 0; !ret && i < msg->len; i++) {
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/* disable ACK for final READ */
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if (i == msg->len - 1)
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clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
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read_write_byte(i2c);
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ret = WaitForXfer(i2c);
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msg->buf[i] = readl(&i2c->iicds);
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}
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if (ret == I2C_NACK)
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ret = I2C_OK; /* Normal terminated read */
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} else {
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for (i = 0; !ret && i < msg->len; i++) {
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writel(msg->buf[i], &i2c->iicds);
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read_write_byte(i2c);
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ret = WaitForXfer(i2c);
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}
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}
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err:
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return ret;
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}
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static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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struct s3c24x0_i2c *i2c = i2c_bus->regs;
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ulong start_time;
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int ret, i;
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start_time = get_timer(0);
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while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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if (get_timer(start_time) > I2C_TIMEOUT_MS) {
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debug("Timeout\n");
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return -ETIMEDOUT;
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}
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}
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for (ret = 0, i = 0; !ret && i < nmsgs; i++)
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ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
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/* Send STOP */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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read_write_byte(i2c);
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return ret ? -EREMOTEIO : 0;
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}
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static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
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{
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const void *blob = gd->fdt_blob;
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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int node;
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node = dev_of_offset(dev);
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i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
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i2c_bus->id = pinmux_decode_periph_id(blob, node);
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i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
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"clock-frequency", 100000);
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i2c_bus->node = node;
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i2c_bus->bus_num = dev->seq;
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exynos_pinmux_config(i2c_bus->id, 0);
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i2c_bus->active = true;
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return 0;
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}
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static const struct dm_i2c_ops s3c_i2c_ops = {
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.xfer = s3c24x0_i2c_xfer,
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.probe_chip = s3c24x0_i2c_probe,
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.set_bus_speed = s3c24x0_i2c_set_bus_speed,
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};
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static const struct udevice_id s3c_i2c_ids[] = {
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{ .compatible = "samsung,s3c2440-i2c" },
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{ }
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};
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U_BOOT_DRIVER(i2c_s3c) = {
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.name = "i2c_s3c",
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.id = UCLASS_I2C,
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.of_match = s3c_i2c_ids,
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.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
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.ops = &s3c_i2c_ops,
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};
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