upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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656 lines
16 KiB
656 lines
16 KiB
/*
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* Copyright 2004-2008 Freescale Semiconductor, Inc.
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* Copyright 2009 Semihalf.
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>
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*
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* Based on original driver from Freescale Semiconductor
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* written by John Rigby <jrigby@freescale.com> on basis
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* of drivers/mtd/nand/mxc_nand.c. Reworked and extended
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* Piotr Ziecik <kosmo@semihalf.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/compat.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <nand.h>
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#define DRV_NAME "mpc5121_nfc"
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/* Timeouts */
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#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
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#define NFC_TIMEOUT 2000 /* 2000 us */
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/* Addresses for NFC MAIN RAM BUFFER areas */
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#define NFC_MAIN_AREA(n) ((n) * 0x200)
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/* Addresses for NFC SPARE BUFFER areas */
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#define NFC_SPARE_BUFFERS 8
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#define NFC_SPARE_LEN 0x40
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#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
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/* MPC5121 NFC registers */
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#define NFC_BUF_ADDR 0x1E04
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#define NFC_FLASH_ADDR 0x1E06
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#define NFC_FLASH_CMD 0x1E08
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#define NFC_CONFIG 0x1E0A
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#define NFC_ECC_STATUS1 0x1E0C
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#define NFC_ECC_STATUS2 0x1E0E
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#define NFC_SPAS 0x1E10
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#define NFC_WRPROT 0x1E12
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#define NFC_NF_WRPRST 0x1E18
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#define NFC_CONFIG1 0x1E1A
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#define NFC_CONFIG2 0x1E1C
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#define NFC_UNLOCKSTART_BLK0 0x1E20
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#define NFC_UNLOCKEND_BLK0 0x1E22
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#define NFC_UNLOCKSTART_BLK1 0x1E24
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#define NFC_UNLOCKEND_BLK1 0x1E26
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#define NFC_UNLOCKSTART_BLK2 0x1E28
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#define NFC_UNLOCKEND_BLK2 0x1E2A
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#define NFC_UNLOCKSTART_BLK3 0x1E2C
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#define NFC_UNLOCKEND_BLK3 0x1E2E
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/* Bit Definitions: NFC_BUF_ADDR */
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#define NFC_RBA_MASK (7 << 0)
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#define NFC_ACTIVE_CS_SHIFT 5
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#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
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/* Bit Definitions: NFC_CONFIG */
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#define NFC_BLS_UNLOCKED (1 << 1)
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/* Bit Definitions: NFC_CONFIG1 */
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#define NFC_ECC_4BIT (1 << 0)
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#define NFC_FULL_PAGE_DMA (1 << 1)
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#define NFC_SPARE_ONLY (1 << 2)
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#define NFC_ECC_ENABLE (1 << 3)
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#define NFC_INT_MASK (1 << 4)
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#define NFC_BIG_ENDIAN (1 << 5)
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#define NFC_RESET (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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#define NFC_PPB_32 (0 << 9)
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#define NFC_PPB_64 (1 << 9)
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#define NFC_PPB_128 (2 << 9)
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#define NFC_PPB_256 (3 << 9)
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#define NFC_PPB_MASK (3 << 9)
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#define NFC_FULL_PAGE_INT (1 << 11)
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/* Bit Definitions: NFC_CONFIG2 */
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#define NFC_COMMAND (1 << 0)
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#define NFC_ADDRESS (1 << 1)
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#define NFC_INPUT (1 << 2)
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#define NFC_OUTPUT (1 << 3)
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#define NFC_ID (1 << 4)
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#define NFC_STATUS (1 << 5)
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#define NFC_CMD_FAIL (1 << 15)
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#define NFC_INT (1 << 15)
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/* Bit Definitions: NFC_WRPROT */
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#define NFC_WPC_LOCK_TIGHT (1 << 0)
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#define NFC_WPC_LOCK (1 << 1)
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#define NFC_WPC_UNLOCK (1 << 2)
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struct mpc5121_nfc_prv {
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struct nand_chip chip;
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int irq;
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void __iomem *regs;
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struct clk *clk;
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uint column;
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int spareonly;
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int chipsel;
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};
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int mpc5121_nfc_chip = 0;
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static void mpc5121_nfc_done(struct mtd_info *mtd);
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/* Read NFC register */
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static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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return in_be16(prv->regs + reg);
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}
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/* Write NFC register */
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static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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out_be16(prv->regs + reg, val);
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}
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/* Set bits in NFC register */
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static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
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{
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nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
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}
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/* Clear bits in NFC register */
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static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
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{
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nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
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}
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/* Invoke address cycle */
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static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
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{
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nfc_write(mtd, NFC_FLASH_ADDR, addr);
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nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
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mpc5121_nfc_done(mtd);
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}
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/* Invoke command cycle */
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static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
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{
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nfc_write(mtd, NFC_FLASH_CMD, cmd);
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nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
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mpc5121_nfc_done(mtd);
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}
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/* Send data from NFC buffers to NAND flash */
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static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
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mpc5121_nfc_done(mtd);
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}
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/* Receive data from NAND flash */
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static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
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mpc5121_nfc_done(mtd);
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}
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/* Receive ID from NAND flash */
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static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_ID);
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mpc5121_nfc_done(mtd);
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}
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/* Receive status from NAND flash */
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static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
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mpc5121_nfc_done(mtd);
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}
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static void mpc5121_nfc_done(struct mtd_info *mtd)
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{
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int max_retries = NFC_TIMEOUT;
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while (1) {
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max_retries--;
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if (nfc_read(mtd, NFC_CONFIG2) & NFC_INT)
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break;
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udelay(1);
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}
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if (max_retries <= 0)
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printk(KERN_WARNING DRV_NAME
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": Timeout while waiting for completion.\n");
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}
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/* Do address cycle(s) */
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static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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u32 pagemask = chip->pagemask;
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if (column != -1) {
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mpc5121_nfc_send_addr(mtd, column);
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if (mtd->writesize > 512)
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mpc5121_nfc_send_addr(mtd, column >> 8);
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}
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if (page != -1) {
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do {
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mpc5121_nfc_send_addr(mtd, page & 0xFF);
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page >>= 8;
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pagemask >>= 8;
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} while (pagemask);
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}
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}
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/* Control chip select signals */
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/*
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* Selecting the active device:
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*
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* This is different than the linux version. Switching between chips
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* is done via board_nand_select_device(). The Linux select_chip
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* function used here in U-Boot has only 2 valid chip numbers:
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* 0 select
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* -1 deselect
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*/
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/*
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* Implement it as a weak default, so that boards with a specific
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* chip-select routine can use their own function.
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*/
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void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
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{
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if (chip < 0) {
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nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
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return;
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}
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
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nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
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NFC_ACTIVE_CS_MASK);
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nfc_set(mtd, NFC_CONFIG1, NFC_CE);
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}
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void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
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__attribute__((weak, alias("__mpc5121_nfc_select_chip")));
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void board_nand_select_device(struct nand_chip *nand, int chip)
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{
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/*
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* Only save this chip number in global variable here. This
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* will be used later in mpc5121_nfc_select_chip().
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*/
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mpc5121_nfc_chip = chip;
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}
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/* Read NAND Ready/Busy signal */
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static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
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{
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/*
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* NFC handles ready/busy signal internally. Therefore, this function
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* always returns status as ready.
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*/
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return 1;
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}
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/* Write command to NAND flash */
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static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
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int column, int page)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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prv->column = (column >= 0) ? column : 0;
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prv->spareonly = 0;
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switch (command) {
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case NAND_CMD_PAGEPROG:
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mpc5121_nfc_send_prog_page(mtd);
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break;
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/*
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* NFC does not support sub-page reads and writes,
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* so emulate them using full page transfers.
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*/
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case NAND_CMD_READ0:
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column = 0;
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break;
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case NAND_CMD_READ1:
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prv->column += 256;
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command = NAND_CMD_READ0;
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column = 0;
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break;
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case NAND_CMD_READOOB:
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prv->spareonly = 1;
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command = NAND_CMD_READ0;
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column = 0;
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break;
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case NAND_CMD_SEQIN:
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mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
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column = 0;
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break;
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_READID:
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case NAND_CMD_STATUS:
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case NAND_CMD_RESET:
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break;
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default:
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return;
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}
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mpc5121_nfc_send_cmd(mtd, command);
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mpc5121_nfc_addr_cycle(mtd, column, page);
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switch (command) {
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case NAND_CMD_READ0:
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if (mtd->writesize > 512)
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mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
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mpc5121_nfc_send_read_page(mtd);
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break;
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case NAND_CMD_READID:
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mpc5121_nfc_send_read_id(mtd);
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break;
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case NAND_CMD_STATUS:
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mpc5121_nfc_send_read_status(mtd);
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if (chip->options & NAND_BUSWIDTH_16)
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prv->column = 1;
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else
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prv->column = 0;
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break;
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}
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}
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/* Copy data from/to NFC spare buffers. */
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static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
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u8 * buffer, uint size, int wr)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
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uint o, s, sbsize, blksize;
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/*
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* NAND spare area is available through NFC spare buffers.
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* The NFC divides spare area into (page_size / 512) chunks.
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* Each chunk is placed into separate spare memory area, using
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* first (spare_size / num_of_chunks) bytes of the buffer.
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*
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* For NAND device in which the spare area is not divided fully
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* by the number of chunks, number of used bytes in each spare
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* buffer is rounded down to the nearest even number of bytes,
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* and all remaining bytes are added to the last used spare area.
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*
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* For more information read section 26.6.10 of MPC5121e
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* Microcontroller Reference Manual, Rev. 3.
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*/
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/* Calculate number of valid bytes in each spare buffer */
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sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
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while (size) {
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/* Calculate spare buffer number */
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s = offset / sbsize;
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if (s > NFC_SPARE_BUFFERS - 1)
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s = NFC_SPARE_BUFFERS - 1;
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/*
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* Calculate offset to requested data block in selected spare
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* buffer and its size.
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*/
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o = offset - (s * sbsize);
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blksize = min(sbsize - o, size);
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if (wr)
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memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
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buffer, blksize);
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else
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memcpy_fromio(buffer,
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prv->regs + NFC_SPARE_AREA(s) + o,
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blksize);
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buffer += blksize;
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offset += blksize;
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size -= blksize;
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};
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}
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/* Copy data from/to NFC main and spare buffers */
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static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len,
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int wr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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uint c = prv->column;
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uint l;
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/* Handle spare area access */
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if (prv->spareonly || c >= mtd->writesize) {
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/* Calculate offset from beginning of spare area */
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if (c >= mtd->writesize)
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c -= mtd->writesize;
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prv->column += len;
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mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
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return;
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}
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/*
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* Handle main area access - limit copy length to prevent
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* crossing main/spare boundary.
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*/
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l = min((uint) len, mtd->writesize - c);
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prv->column += l;
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if (wr)
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memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
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else
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memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
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/* Handle crossing main/spare boundary */
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if (l != len) {
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buf += l;
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len -= l;
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mpc5121_nfc_buf_copy(mtd, buf, len, wr);
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}
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}
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/* Read data from NFC buffers */
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static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char * buf, int len)
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{
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mpc5121_nfc_buf_copy(mtd, buf, len, 0);
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}
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/* Write data to NFC buffers */
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static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
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const u_char * buf, int len)
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{
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mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1);
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}
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/* Read byte from NFC buffers */
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static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
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{
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u8 tmp;
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mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
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return tmp;
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}
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/* Read word from NFC buffers */
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static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
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{
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u16 tmp;
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mpc5121_nfc_read_buf(mtd, (u_char *) & tmp, sizeof(tmp));
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return tmp;
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}
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/*
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* Read NFC configuration from Reset Config Word
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*
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* NFC is configured during reset in basis of information stored
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* in Reset Config Word. There is no other way to set NAND block
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* size, spare size and bus width.
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*/
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static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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struct nand_chip *chip = mtd_to_nand(mtd);
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uint rcw_pagesize = 0;
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uint rcw_sparesize = 0;
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uint rcw_width;
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uint rcwh;
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uint romloc, ps;
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rcwh = in_be32(&(im->reset.rcwh));
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/* Bit 6: NFC bus width */
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rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
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/* Bit 7: NFC Page/Spare size */
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ps = (rcwh >> 7) & 0x1;
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/* Bits [22:21]: ROM Location */
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romloc = (rcwh >> 21) & 0x3;
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/* Decode RCW bits */
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switch ((ps << 2) | romloc) {
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case 0x00:
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case 0x01:
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rcw_pagesize = 512;
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rcw_sparesize = 16;
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break;
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case 0x02:
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case 0x03:
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rcw_pagesize = 4096;
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rcw_sparesize = 128;
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break;
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case 0x04:
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case 0x05:
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rcw_pagesize = 2048;
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rcw_sparesize = 64;
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break;
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case 0x06:
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case 0x07:
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rcw_pagesize = 4096;
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rcw_sparesize = 218;
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break;
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}
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mtd->writesize = rcw_pagesize;
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mtd->oobsize = rcw_sparesize;
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if (rcw_width == 2)
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chip->options |= NAND_BUSWIDTH_16;
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debug(KERN_NOTICE DRV_NAME ": Configured for "
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"%u-bit NAND, page size %u with %u spare.\n",
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rcw_width * 8, rcw_pagesize, rcw_sparesize);
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return 0;
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}
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int board_nand_init(struct nand_chip *chip)
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{
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struct mpc5121_nfc_prv *prv;
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struct mtd_info *mtd;
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int resettime = 0;
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int retval = 0;
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int rev;
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/*
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* Check SoC revision. This driver supports only NFC
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* in MPC5121 revision 2.
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*/
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rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
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if (rev != 2) {
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printk(KERN_ERR DRV_NAME
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": SoC revision %u is not supported!\n", rev);
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return -ENXIO;
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}
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prv = malloc(sizeof(*prv));
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if (!prv) {
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printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
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return -ENOMEM;
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}
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mtd = &chip->mtd;
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nand_set_controller_data(chip, prv);
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/* Read NFC configuration from Reset Config Word */
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retval = mpc5121_nfc_read_hw_config(mtd);
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if (retval) {
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printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
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return retval;
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}
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prv->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
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chip->dev_ready = mpc5121_nfc_dev_ready;
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chip->cmdfunc = mpc5121_nfc_command;
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chip->read_byte = mpc5121_nfc_read_byte;
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chip->read_word = mpc5121_nfc_read_word;
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chip->read_buf = mpc5121_nfc_read_buf;
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chip->write_buf = mpc5121_nfc_write_buf;
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chip->select_chip = mpc5121_nfc_select_chip;
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chip->bbt_options = NAND_BBT_USE_FLASH;
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chip->ecc.mode = NAND_ECC_SOFT;
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/* Reset NAND Flash controller */
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nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
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while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
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if (resettime++ >= NFC_RESET_TIMEOUT) {
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printk(KERN_ERR DRV_NAME
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": Timeout while resetting NFC!\n");
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retval = -EINVAL;
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goto error;
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}
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udelay(1);
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}
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/* Enable write to NFC memory */
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nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
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/* Enable write to all NAND pages */
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nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
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nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
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nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
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/*
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* Setup NFC:
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* - Big Endian transfers,
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* - Interrupt after full page read/write.
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*/
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nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
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NFC_FULL_PAGE_INT);
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/* Set spare area size */
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nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
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/* Detect NAND chips */
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if (nand_scan(mtd, 1)) {
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printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
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retval = -ENXIO;
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goto error;
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}
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/* Set erase block size */
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switch (mtd->erasesize / mtd->writesize) {
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case 32:
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nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
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break;
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case 64:
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nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
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break;
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case 128:
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nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
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break;
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case 256:
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nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
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break;
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default:
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printk(KERN_ERR DRV_NAME ": Unsupported NAND flash!\n");
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retval = -ENXIO;
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goto error;
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}
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return 0;
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error:
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return retval;
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}
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