upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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118 lines
3.0 KiB
118 lines
3.0 KiB
/*
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* SAMSUNG EXYNOS USB HOST EHCI Controller
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* Vivek Gautam <gautam.vivek@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ehci.h>
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#include <asm/arch/system.h>
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#include <asm/arch/power.h>
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#include "ehci.h"
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#include "ehci-core.h"
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/* Setup the EHCI host controller. */
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static void setup_usb_phy(struct exynos_usb_phy *usb)
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{
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set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
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set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
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clrbits_le32(&usb->usbphyctrl0,
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HOST_CTRL0_FSEL_MASK |
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HOST_CTRL0_COMMONON_N |
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/* HOST Phy setting */
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HOST_CTRL0_PHYSWRST |
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HOST_CTRL0_PHYSWRSTALL |
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HOST_CTRL0_SIDDQ |
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HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP);
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setbits_le32(&usb->usbphyctrl0,
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/* Setting up the ref freq */
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(CLK_24MHZ << 16) |
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/* HOST Phy setting */
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HOST_CTRL0_LINKSWRST |
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HOST_CTRL0_UTMISWRST);
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udelay(10);
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clrbits_le32(&usb->usbphyctrl0,
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HOST_CTRL0_LINKSWRST |
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HOST_CTRL0_UTMISWRST);
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udelay(20);
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/* EHCI Ctrl setting */
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setbits_le32(&usb->ehcictrl,
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EHCICTRL_ENAINCRXALIGN |
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EHCICTRL_ENAINCR4 |
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EHCICTRL_ENAINCR8 |
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EHCICTRL_ENAINCR16);
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}
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/* Reset the EHCI host controller. */
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static void reset_usb_phy(struct exynos_usb_phy *usb)
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{
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/* HOST_PHY reset */
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setbits_le32(&usb->usbphyctrl0,
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HOST_CTRL0_PHYSWRST |
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HOST_CTRL0_PHYSWRSTALL |
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HOST_CTRL0_SIDDQ |
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HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP);
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set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
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}
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/*
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* EHCI-initialization
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*/
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int ehci_hcd_init(void)
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{
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struct exynos_usb_phy *usb;
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usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
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setup_usb_phy(usb);
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hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
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hcor = (struct ehci_hcor *)((uint32_t) hccr
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+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)hccr, (uint32_t)hcor,
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(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the EHCI host controller.
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*/
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int ehci_hcd_stop()
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{
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struct exynos_usb_phy *usb;
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usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
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reset_usb_phy(usb);
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return 0;
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}
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