upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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572 lines
15 KiB
572 lines
15 KiB
/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx51.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/spi.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <power/pmic.h>
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#include <fsl_esdhc.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct fb_videomode const nec_nl6448bc26_09c = {
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"NEC_NL6448BC26-09C",
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60, /* Refresh */
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640, /* xres */
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480, /* yres */
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37650, /* pixclock = 26.56Mhz */
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48, /* left margin */
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16, /* right margin */
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31, /* upper margin */
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12, /* lower margin */
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96, /* hsync-len */
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2, /* vsync-len */
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0, /* sync */
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FB_VMODE_NONINTERLACED, /* vmode */
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0, /* flag */
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};
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#ifdef CONFIG_HW_WATCHDOG
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#include <watchdog.h>
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void hw_watchdog_reset(void)
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{
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int val;
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/* toggle watchdog trigger pin */
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val = gpio_get_value(IMX_GPIO_NR(3, 2));
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val = val ? 0 : 1;
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gpio_set_value(IMX_GPIO_NR(3, 2), val);
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}
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#endif
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static void init_drive_strength(void)
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{
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static const iomux_v3_cfg_t ddr_pads[] = {
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NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
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NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
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NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
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NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
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NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
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NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
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NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_weim(void)
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{
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struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
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pweim->cs0gcr1 = 0x004100b9;
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pweim->cs0gcr2 = 0x00000001;
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pweim->cs0rcr1 = 0x0a018000;
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pweim->cs0rcr2 = 0;
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pweim->cs0wcr1 = 0x0704a240;
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}
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static void setup_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
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MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_MXC_SPI
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == 0 && cs == 1) ? 121 : -1;
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}
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void spi_io_init(void)
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{
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static const iomux_v3_cfg_t spi_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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};
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
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}
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static void reset_peripherals(int reset)
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{
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#ifdef CONFIG_VISION2_HW_1_0
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static const iomux_v3_cfg_t fec_cfg_pads[] = {
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/* RXD1 */
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
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/* RXD2 */
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
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/* RXD3 */
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
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/* RXER */
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NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
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/* COL */
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
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/* RCLK */
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
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/* RXD0 */
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NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
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};
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
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MX51_PAD_NANDF_D9__FEC_RDATA0,
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
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};
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#endif
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if (reset) {
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/* reset_n is on NANDF_D15 */
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gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
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#ifdef CONFIG_VISION2_HW_1_0
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/*
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* set FEC Configuration lines
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* set levels of FEC config lines
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*/
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gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
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gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
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gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
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/* set direction of FEC config lines */
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gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
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gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
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gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
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gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
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imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
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ARRAY_SIZE(fec_cfg_pads));
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#endif
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/* activate reset_n pin */
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imx_iomux_v3_setup_pad(
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NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
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PAD_CTL_DSE_MAX));
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} else {
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/* set FEC Control lines */
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gpio_direction_input(IMX_GPIO_NR(3, 25));
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udelay(500);
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#ifdef CONFIG_VISION2_HW_1_0
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imx_iomux_v3_setup_multiple_pads(fec_pads,
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ARRAY_SIZE(fec_pads));
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#endif
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}
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}
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static void power_init_mx51(void)
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{
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unsigned int val;
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struct pmic *p;
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int ret;
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ret = pmic_init(I2C_PMIC);
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if (ret)
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return;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return;
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/* Write needed to Power Gate 2 register */
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pmic_reg_read(p, REG_POWER_MISC, &val);
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/* enable VCAM with 2.775V to enable read from PMIC */
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val = VCAMCONFIG | VCAMEN;
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pmic_reg_write(p, REG_MODE_1, val);
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/*
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* Set switchers in Auto in NORMAL mode & STANDBY mode
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* Setup the switcher mode for SW1 & SW2
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*/
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pmic_reg_read(p, REG_SW_4, &val);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(p, REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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pmic_reg_read(p, REG_SW_5, &val);
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val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
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(SWMODE_MASK << SWMODE3_SHIFT));
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val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
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pmic_reg_write(p, REG_SW_5, val);
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/* Set VGEN3 to 1.8V, VCAM to 3.0V */
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pmic_reg_read(p, REG_SETTING_0, &val);
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val &= ~(VCAM_MASK | VGEN3_MASK);
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val |= VCAM_3_0;
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pmic_reg_write(p, REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
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pmic_reg_read(p, REG_SETTING_1, &val);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
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pmic_reg_write(p, REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(p, REG_MODE_1, val);
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udelay(200);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
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VVIDEOEN | VAUDIOEN | VSDEN;
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pmic_reg_write(p, REG_MODE_1, val);
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pmic_reg_read(p, REG_POWER_CTL2, &val);
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val |= WDIRESET;
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pmic_reg_write(p, REG_POWER_CTL2, val);
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udelay(2500);
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}
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#endif
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static void setup_gpios(void)
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{
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static const iomux_v3_cfg_t gpio_pads_1[] = {
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NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
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NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* DAB Display EN */
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NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
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};
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static const iomux_v3_cfg_t gpio_pads_2[] = {
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NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* Display2 TxEN */
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NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* DAB Light EN */
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NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* AUDIO_MUTE */
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NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* SPARE_OUT */
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NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* BEEPER_EN */
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NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* POWER_OFF */
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NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* FRAM_WE */
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NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
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PAD_CTL_DSE_MED), /* EXPANSION_EN */
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MX51_PAD_GPIO1_2__PWM1_PWMO,
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};
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unsigned int i;
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imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
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/* Now we need to trigger the watchdog */
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WATCHDOG_RESET();
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imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
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/*
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* Set GPIO1_4 to high and output; it is used to reset
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* the system on reboot
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*/
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gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
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gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
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for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
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gpio_direction_output(i, 0);
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gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
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/* Set POWER_OFF high */
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gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
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gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
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gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
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gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
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WATCHDOG_RESET();
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}
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static void setup_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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MX51_PAD_NANDF_CS3__FEC_MDC,
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
|
|
MX51_PAD_NANDF_D9__FEC_RDATA0,
|
|
MX51_PAD_NANDF_CS6__FEC_TDATA3,
|
|
MX51_PAD_NANDF_CS5__FEC_TDATA2,
|
|
MX51_PAD_NANDF_CS4__FEC_TDATA1,
|
|
MX51_PAD_NANDF_D8__FEC_TDATA0,
|
|
MX51_PAD_NANDF_CS7__FEC_TX_EN,
|
|
MX51_PAD_NANDF_CS2__FEC_TX_ER,
|
|
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
|
|
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
|
|
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
|
|
MX51_PAD_EIM_CS5__FEC_CRS,
|
|
MX51_PAD_EIM_CS4__FEC_RX_ER,
|
|
NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
|
|
};
|
|
|
|
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
|
}
|
|
|
|
struct fsl_esdhc_cfg esdhc_cfg[1] = {
|
|
{MMC_SDHC1_BASE_ADDR},
|
|
};
|
|
|
|
int get_mmc_getcd(u8 *cd, struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
|
|
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
|
*cd = gpio_get_value(IMX_GPIO_NR(1, 0));
|
|
else
|
|
*cd = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
static const iomux_v3_cfg_t sd1_pads[] = {
|
|
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
|
|
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
|
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
|
|
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
|
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
|
|
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
|
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
|
|
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
|
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
|
|
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
|
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
|
|
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
|
|
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
|
|
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
|
|
};
|
|
|
|
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
|
|
|
|
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
|
}
|
|
#endif
|
|
|
|
void lcd_enable(void)
|
|
{
|
|
static const iomux_v3_cfg_t lcd_pads[] = {
|
|
MX51_PAD_DI1_PIN2__DI1_PIN2,
|
|
MX51_PAD_DI1_PIN3__DI1_PIN3,
|
|
};
|
|
|
|
int ret;
|
|
|
|
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
|
|
|
gpio_set_value(IMX_GPIO_NR(1, 2), 1);
|
|
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
|
|
NO_PAD_CTRL));
|
|
|
|
ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
|
|
if (ret)
|
|
puts("LCD cannot be configured\n");
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
|
|
|
|
init_drive_strength();
|
|
|
|
/* Setup debug led */
|
|
gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
|
|
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
|
|
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
|
|
|
|
/* wait a little while to give the pll time to settle */
|
|
sdelay(100000);
|
|
|
|
setup_weim();
|
|
setup_uart();
|
|
setup_fec();
|
|
setup_gpios();
|
|
|
|
spi_io_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void backlight(int on)
|
|
{
|
|
if (on) {
|
|
gpio_set_value(IMX_GPIO_NR(3, 1), 1);
|
|
udelay(10000);
|
|
gpio_set_value(IMX_GPIO_NR(3, 4), 1);
|
|
} else {
|
|
gpio_set_value(IMX_GPIO_NR(3, 1), 0);
|
|
gpio_set_value(IMX_GPIO_NR(3, 4), 0);
|
|
}
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
lcd_enable();
|
|
|
|
backlight(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
power_init_mx51();
|
|
|
|
reset_peripherals(1);
|
|
udelay(2000);
|
|
reset_peripherals(0);
|
|
udelay(2000);
|
|
|
|
/* Early revisions require a second reset */
|
|
#ifdef CONFIG_VISION2_HW_1_0
|
|
reset_peripherals(1);
|
|
udelay(2000);
|
|
reset_peripherals(0);
|
|
udelay(2000);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Do not overwrite the console
|
|
* Use always serial for U-Boot console
|
|
*/
|
|
int overwrite_console(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: TTControl Vision II CPU V\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
int on;
|
|
|
|
if (argc < 2)
|
|
return cmd_usage(cmdtp);
|
|
|
|
on = (strcmp(argv[1], "on") == 0);
|
|
backlight(on);
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
|
|
"Vision2 Backlight",
|
|
"lcdbl [on|off]\n"
|
|
);
|
|
|