upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.4 KiB
59 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Author: Roy Zang <tie-fei.zang@freescale.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x00] = {PCIE1, PCIE2, NONE, NONE},
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[0x01] = {PCIE1, PCIE2, PCIE3, NONE},
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[0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2},
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[0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2},
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret;
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if (!(serdes1_prtcl_map & (1 << NONE)))
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fsl_serdes_init();
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ret = (1 << device) & serdes1_prtcl_map;
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return ret;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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if (serdes1_prtcl_map & (1 << NONE))
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return;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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/* Set the first bit to indicate serdes has been initialized */
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serdes1_prtcl_map |= (1 << NONE);
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}
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