upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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120 lines
2.9 KiB
120 lines
2.9 KiB
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <pci.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale FireEngine 5485 EVB\n");
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return 0;
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};
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phys_size_t initdram(int board_type)
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{
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siu_t *siu = (siu_t *) (MMAP_SIU);
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sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
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u32 dramsize, i;
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#ifdef CONFIG_SYS_DRAMSZ1
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u32 temp;
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#endif
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out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
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dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
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#ifdef CONFIG_SYS_DRAMSZ1
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temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (temp == (1 << i))
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break;
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}
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i--;
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dramsize += temp;
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out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
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#endif
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out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
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out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
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/* Issue PALL */
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
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/* Issue LEMR */
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out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
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out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
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udelay(500);
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/* Issue PALL */
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
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/* Perform two refresh cycles */
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
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out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
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out_be32(&sdram->ctrl,
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(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
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udelay(100);
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return dramsize;
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};
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI devices, report devices found.
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*/
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static struct pci_controller hose;
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extern void pci_mcf547x_8x_init(struct pci_controller *hose);
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void pci_init_board(void)
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{
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pci_mcf547x_8x_init(&hose);
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}
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#endif /* CONFIG_PCI */
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