upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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405 lines
11 KiB
405 lines
11 KiB
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <vsc7385.h>
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#ifdef CONFIG_PCI
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#include <asm/mpc8349_pci.h>
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#include <pci.h>
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#endif
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#include <spd_sdram.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#ifndef CONFIG_SPD_EEPROM
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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/* The size of RAM, in bytes */
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u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
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u32 ddr_size_log2 = __ilog2(ddr_size);
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[0].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
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CSBNDS_EA_SHIFT) & CSBNDS_EA);
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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/* Only one CS for DDR */
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[2] = 0;
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im->ddr.cs_config[3] = 0;
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debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
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debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
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debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
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debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
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im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
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im->ddr.sdram_mode =
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(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
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im->ddr.sdram_interval =
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(0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
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SDRAM_INTERVAL_BSTOPRE_SHIFT);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
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debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
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debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
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debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
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debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
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return CONFIG_SYS_DDR_SIZE;
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}
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#endif
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#ifdef CONFIG_PCI
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/*
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* Initialize PCI Devices, report devices found
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
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{
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PCI_ANY_ID,
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PCI_ANY_ID,
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PCI_ANY_ID,
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PCI_ANY_ID,
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0x0f,
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PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{
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PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
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},
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{}
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}
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#endif
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volatile static struct pci_controller hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxmitx_config_table,
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#endif
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},
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxmitx_config_table,
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#endif
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}
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};
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#endif /* CONFIG_PCI */
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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#ifdef CONFIG_DDR_ECC
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volatile ddr83xx_t *ddr = &im->ddr;
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#endif
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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#ifdef CONFIG_SPD_EEPROM
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#ifdef CONFIG_DDR_ECC
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if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
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/* Unlike every other board, on the 83xx spd_sdram() returns
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megabytes instead of just bytes. That's why we need to
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multiple by 1MB when calling ddr_enable_ecc(). */
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ddr_enable_ecc(msize * 1048576);
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#endif
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/* return total bus RAM size(bytes) */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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#ifdef CONFIG_MPC8349ITX
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puts("Board: Freescale MPC8349E-mITX\n");
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#else
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puts("Board: Freescale MPC8349E-mITX-GP\n");
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#endif
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return 0;
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}
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/*
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* Implement a work-around for a hardware problem with compact
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* flash.
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*
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* Program the UPM if compact flash is enabled.
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*/
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int misc_init_f(void)
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{
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#ifdef CONFIG_VSC7385_ENET
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volatile u32 *vsc7385_cpuctrl;
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/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
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default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
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means it is 0 when the IRQ is not active. This makes the wire-AND
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logic always assert IRQ7 to CPU even if there is no request from the
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switch. Since the compact flash and the switch share the same IRQ,
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the Linux kernel will think that the compact flash is requesting irq
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and get stuck when it tries to clear the IRQ. Thus we need to set
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the L2_IRQ0 and L2_IRQ1 to active low.
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The following code sets the L1_IRQ and L2_IRQ polarity to active low.
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Without this code, compact flash will not work in Linux because
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unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
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don't enable compact flash for U-Boot.
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*/
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vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
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*vsc7385_cpuctrl |= 0x0c;
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#endif
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#ifdef CONFIG_COMPACT_FLASH
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/* UPM Table Configuration Code */
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static uint UPMATable[] = {
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0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
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0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
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0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
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};
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
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set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
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/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
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GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
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*/
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immap->im_lbc.mamr = 0x08404440;
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upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
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puts("UPMA: Configured for compact flash\n");
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#endif
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return 0;
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* Make sure the EEPROM has the HRCW correctly programmed.
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* Make sure the RTC is correctly programmed.
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*
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* The MPC8349E-mITX can be configured to load the HRCW from
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* EEPROM instead of flash. This is controlled via jumpers
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* LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
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* jumpered), but if they're set to 001 or 010, then the HRCW is
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* read from the "I2C EEPROM".
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*
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* This function makes sure that the I2C EEPROM is programmed
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* correctly.
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_HARD_I2C
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unsigned int orig_bus = i2c_get_bus_num();
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u8 i2c_data;
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#ifdef CONFIG_SYS_I2C_RTC_ADDR
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u8 ds1339_data[17];
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#endif
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
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static u8 eeprom_data[] = /* HRCW data */
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{
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0xAA, 0x55, 0xAA, /* Preamble */
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0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
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0x02, 0x40, /* RCWL ADDR=0x0_0900 */
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(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
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(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
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(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
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CONFIG_SYS_HRCW_LOW & 0xFF,
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0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
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0x02, 0x41, /* RCWH ADDR=0x0_0904 */
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(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
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(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
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(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
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CONFIG_SYS_HRCW_HIGH & 0xFF
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};
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u8 data[sizeof(eeprom_data)];
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#endif
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printf("Board revision: ");
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i2c_set_bus_num(1);
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if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
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printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
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else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
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printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
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else {
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printf("Unknown\n");
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rc = 1;
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}
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
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i2c_set_bus_num(0);
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
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if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
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if (i2c_write
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(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
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sizeof(eeprom_data)) != 0) {
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puts("Failure writing the HRCW to EEPROM via I2C.\n");
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rc = 1;
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}
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}
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} else {
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puts("Failure reading the HRCW from EEPROM via I2C.\n");
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rc = 1;
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}
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#endif
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#ifdef CONFIG_SYS_I2C_RTC_ADDR
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i2c_set_bus_num(1);
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if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
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== 0) {
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/* Work-around for MPC8349E-mITX bug #13601.
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If the RTC does not contain valid register values, the DS1339
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Linux driver will not work.
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*/
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/* Make sure status register bits 6-2 are zero */
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ds1339_data[0x0f] &= ~0x7c;
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/* Check for a valid day register value */
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ds1339_data[0x03] &= ~0xf8;
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if (ds1339_data[0x03] == 0) {
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ds1339_data[0x03] = 1;
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}
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/* Check for a valid date register value */
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ds1339_data[0x04] &= ~0xc0;
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if ((ds1339_data[0x04] == 0) ||
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((ds1339_data[0x04] & 0x0f) > 9) ||
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(ds1339_data[0x04] >= 0x32)) {
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ds1339_data[0x04] = 1;
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}
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/* Check for a valid month register value */
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ds1339_data[0x05] &= ~0x60;
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if ((ds1339_data[0x05] == 0) ||
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((ds1339_data[0x05] & 0x0f) > 9) ||
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((ds1339_data[0x05] >= 0x13)
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&& (ds1339_data[0x05] <= 0x19))) {
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ds1339_data[0x05] = 1;
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}
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/* Enable Oscillator and rate select */
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ds1339_data[0x0e] = 0x1c;
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/* Work-around for MPC8349E-mITX bug #13330.
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Ensure that the RTC control register contains the value 0x1c.
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This affects SATA performance.
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*/
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if (i2c_write
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(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
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sizeof(ds1339_data))) {
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puts("Failure writing to the RTC via I2C.\n");
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rc = 1;
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}
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} else {
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puts("Failure reading from the RTC via I2C.\n");
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rc = 1;
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}
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#endif
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i2c_set_bus_num(orig_bus);
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#endif
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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