upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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115 lines
4.2 KiB
115 lines
4.2 KiB
# Synology DS109
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_layout_init 0x0008 0x000b
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ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
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ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
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adapter_khz 2000
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# length of reset signal: [ms]
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adapter_nsrst_assert_width 1000
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# don't talk to JTAG after reset for: [ms]
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adapter_nsrst_delay 200
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source [find target/feroceon.cfg]
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reset_config trst_and_srst srst_nogate
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proc ds109_init { } {
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# We need to assert DBGRQ while holding nSRST down.
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# However DBGACK will be set only when nSRST is released.
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# Furthermore, the JTAG interface doesn't respond at all when
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# the CPU is in the WFI (wait for interrupts) state, so it is
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# possible that initial tap examination failed. So let's
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# re-examine the target again here when nSRST is asserted which
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# should then succeed.
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jtag_reset 0 1
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feroceon.cpu arp_examine
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halt 0
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jtag_reset 0 0
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wait_halt
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#reset run
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#soft_reset_halt
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arm mcr 15 0 0 1 0 0x00052078
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mww 0xD00100e0 0x1b1b1b9b ;#
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mww 0xD0020134 0xbbbbbbbb ;#
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mww 0xD0020138 0x00bbbbbb ;#
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mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
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mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
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mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
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mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
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mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
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mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
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mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
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mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
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mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
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mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
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mww 0xD0001428 0x00085520 ;# Dunit Control High Register
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mww 0xD000147c 0x00008552 ;# Dunit Control High Register
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mww 0xD0001500 0x00000000 ;#
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mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register
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mww 0xD0001508 0x10000000 ;# CS1n Base Register
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mww 0xD000150C 0x00000000 ;# CS1n Size Register
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mww 0xD0001510 0x20000000 ;#
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mww 0xD0001514 0x00000000 ;# CS2n Size Register
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mww 0xD000151C 0x00000000 ;# CS3n Size Register
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mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
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mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
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mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
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mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
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mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0020204 0x00000000 ;# "
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mww 0xD0010000 0x01111111 ;# MPP 0 to 7
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mww 0xD0010004 0x11113322 ;# MPP 8 to 15
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mww 0xD0010008 0x00001111 ;# MPP 16 to 23
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}
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proc ds109_load { } {
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# load u-Boot into RAM and execute it
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ds109_init
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load_image u-boot.bin 0x00600000 bin
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resume 0x00600000
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}
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