upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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425 lines
13 KiB
425 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Wandboard
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* Author: Tungyi Lin <tungyilin1127@gmail.com>
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* Richard Hu <hakahu@gmail.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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#if defined(CONFIG_SPL_BUILD)
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#include <asm/arch/mx6-ddr.h>
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/*
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* Driving strength:
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* 0x30 == 40 Ohm
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* 0x28 == 48 Ohm
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*/
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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#define IMX6QP_DRIVE_STRENGTH 0x28
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_cas = IMX6DQ_DRIVE_STRENGTH,
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.dram_ras = IMX6DQ_DRIVE_STRENGTH,
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.dram_reset = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6QP mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
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.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
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.dram_cas = IMX6QP_DRIVE_STRENGTH,
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.dram_ras = IMX6QP_DRIVE_STRENGTH,
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.dram_reset = IMX6QP_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6QP mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6QP_DRIVE_STRENGTH,
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.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_cas = IMX6SDL_DRIVE_STRENGTH,
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.dram_ras = IMX6SDL_DRIVE_STRENGTH,
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.dram_reset = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
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};
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/* H5T04G63AFR-PB */
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static struct mx6_ddr3_cfg h5t04g63afr = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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/* H5TQ2G63DFR-H9 */
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static struct mx6_ddr3_cfg h5tq2g63dfr = {
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.mem_speed = 1333,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1350,
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.trcmin = 4950,
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.trasmin = 3600,
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};
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static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
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.p0_mpwldectrl0 = 0x001f001f,
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.p0_mpwldectrl1 = 0x001f001f,
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.p1_mpwldectrl0 = 0x001f001f,
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.p1_mpwldectrl1 = 0x001f001f,
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.p0_mpdgctrl0 = 0x4301030d,
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.p0_mpdgctrl1 = 0x03020277,
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.p1_mpdgctrl0 = 0x4300030a,
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.p1_mpdgctrl1 = 0x02780248,
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.p0_mprddlctl = 0x4536393b,
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.p1_mprddlctl = 0x36353441,
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.p0_mpwrdlctl = 0x41414743,
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.p1_mpwrdlctl = 0x462f453f,
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};
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/* DDR 64bit 2GB */
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static struct mx6_ddr_sysinfo mem_q = {
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.dsize = 2,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 3, /* 4 refresh commands per refresh cycle */
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};
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static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
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.p0_mpwldectrl0 = 0x001f001f,
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.p0_mpwldectrl1 = 0x001f001f,
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.p1_mpwldectrl0 = 0x001f001f,
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.p1_mpwldectrl1 = 0x001f001f,
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.p0_mpdgctrl0 = 0x420e020e,
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.p0_mpdgctrl1 = 0x02000200,
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.p1_mpdgctrl0 = 0x42020202,
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.p1_mpdgctrl1 = 0x01720172,
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.p0_mprddlctl = 0x494c4f4c,
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.p1_mprddlctl = 0x4a4c4c49,
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.p0_mpwrdlctl = 0x3f3f3133,
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.p1_mpwrdlctl = 0x39373f2e,
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};
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static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
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.p0_mpwldectrl0 = 0x0040003c,
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.p0_mpwldectrl1 = 0x0032003e,
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.p0_mpdgctrl0 = 0x42350231,
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.p0_mpdgctrl1 = 0x021a0218,
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.p0_mprddlctl = 0x4b4b4e49,
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.p0_mpwrdlctl = 0x3f3f3035,
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};
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/* DDR 64bit 1GB */
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static struct mx6_ddr_sysinfo mem_dl = {
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.dsize = 2,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 3, /* 4 refresh commands per refresh cycle */
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};
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/* DDR 32bit 512MB */
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static struct mx6_ddr_sysinfo mem_s = {
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.dsize = 1,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 3, /* 4 refresh commands per refresh cycle */
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF03000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void spl_dram_init_imx6qp_lpddr3(void)
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{
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/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
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writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
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/* Calibrations - ZQ */
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writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
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/* write leveling */
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writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
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writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
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writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
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writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
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/*
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* DQS gating, read delay, write delay calibration values
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* based on calibration compare of 0x00ffff00
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*/
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writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
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writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
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writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
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writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
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writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
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writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
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writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
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writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
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writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
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writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
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writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
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writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
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/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
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writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
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writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
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writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
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writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
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writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
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writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
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writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
|
|
writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
|
|
writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
|
|
writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
|
|
writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
|
|
writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
|
|
/* add NOC DDR configuration */
|
|
writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
|
|
writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
|
|
writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
|
|
writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
|
|
writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
|
|
writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
|
|
writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
|
|
writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
|
|
writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
|
|
writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
|
|
writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
|
|
writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
|
|
writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
|
|
writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
|
|
writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
|
|
writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
|
|
writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
if (is_mx6dqp()) {
|
|
mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
|
|
spl_dram_init_imx6qp_lpddr3();
|
|
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
|
|
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
|
|
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
|
|
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
|
|
} else if (is_cpu_type(MXC_CPU_MX6Q)) {
|
|
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
|
|
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
|
|
}
|
|
|
|
udelay(100);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
ccgr_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
gpr_init();
|
|
|
|
/* iomux */
|
|
board_early_init_f();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
}
|
|
#endif
|
|
|