upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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165 lines
3.7 KiB
165 lines
3.7 KiB
/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000-2003 Wolfgang Denk <wd@denx.de>
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* Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include "version.h"
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#endif
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#define MCF_MBAR 0x10000000
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#define MEM_BUILTIN_ADDR 0x20000000
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#define MEM_BUILTIN_SIZE 0x1000
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#define DRAM_ADDR 0x0
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#define DRAM_SIZE 0x400000
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.text
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.globl _start
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_start:
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nop
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nop
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move.w #0x2700,%sr
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move.l #0, %d0
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movec %d0, %VBR
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#ifdef CONFIG_M5272
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move.l #(MCF_MBAR+1), %d0
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move.c %d0, %MBAR
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move.l #(MEM_BUILTIN_ADDR+1), %d0
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movec %d0, %RAMBAR0
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move.l #0x01000000, %d0 /* Invalidate cache cmd */
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movec %d0, %CACR /* Invalidate cache */
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move.l #0x0000c000, %d0 /* Setup cache mask */
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movec %d0, %ACR0 /* Enable cache */
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move.l #0xff00c000, %d0 /* Setup cache mask */
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movec %d0, %ACR1 /* Enable cache */
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move.l #0x80000100, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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#endif
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move.l #_sbss,%a0
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move.l #_ebss,%d0
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1:
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clr.l (%a0)+
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cmp.l %a0,%d0
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bne.s 1b
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/* move.l #MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
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move.l #DRAM_ADDR+DRAM_SIZE, %sp
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clr.l %sp@-
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jsr board_init_f
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.globl exception_handler
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exception_handler:
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move.w #0x2700,%sr
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lea %sp@(-60),%sp
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movem.l %d0-%d7/%a0-%a6,%sp@
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jsr do_exception
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movem.l %sp@,%d0-%d7/%a0-%a6
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lea %sp@(60),%sp
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rte
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.globl buserror_handler
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buserror_handler:
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move.w #0x2700,%sr
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lea %sp@(-60),%sp
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movem.l %d0-%d7/%a0-%a6,%sp@
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jsr do_buserror
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movem.l %sp@,%d0-%d7/%a0-%a6
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lea %sp@(60),%sp
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rte
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.globl addresserror_handler
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addresserror_handler:
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move.w #0x2700,%sr
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lea %sp@(-60),%sp
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movem.l %d0-%d7/%a0-%a6,%sp@
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jsr do_buserror
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movem.l %sp@,%d0-%d7/%a0-%a6
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lea %sp@(60),%sp
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rte
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.globl get_endaddr
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get_endaddr:
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movel #_end,%d0
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rts
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#ifdef CONFIG_M5272
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.globl icache_enable
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icache_enable:
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move.l #0x01000000, %d0 /* Invalidate cache cmd */
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movec %d0, %CACR /* Invalidate cache */
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move.l #0x0000c000, %d0 /* Setup cache mask */
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movec %d0, %ACR0 /* Enable cache */
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move.l #0xff00c000, %d0 /* Setup cache mask */
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movec %d0, %ACR1 /* Enable cache */
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move.l #0x80000100, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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moveq #1, %d0
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move.l %d0, icache_state
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rts
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.globl icache_disable
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icache_disable:
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move.l #0x00000100, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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clr.l %d0 /* Setup cache mask */
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movec %d0, %ACR0 /* Enable cache */
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movec %d0, %ACR1 /* Enable cache */
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moveq #0, %d0
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move.l %d0, icache_state
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rts
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#endif
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#ifdef CONFIG_M5282
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.globl icache_enable
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icache_enable:
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rts
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.globl icache_disable
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icache_disable:
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rts
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#endif
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.globl icache_status
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icache_status:
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move.l icache_state, %d0
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rts
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.data
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icache_state:
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.long 1
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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