upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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106 lines
2.2 KiB
106 lines
2.2 KiB
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#define ZYNQ_SILICON_VER_MASK 0xF000
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#define ZYNQ_SILICON_VER_SHIFT 12
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region zynqmp_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x70000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x07e00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0xffe00000UL,
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.phys = 0xffe00000UL,
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.size = 0x00200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x400000000UL,
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.phys = 0x400000000UL,
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.size = 0x200000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x600000000UL,
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.phys = 0x600000000UL,
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.size = 0x800000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xe00000000UL,
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.phys = 0xe00000000UL,
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.size = 0xf200000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = zynqmp_mem_map;
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u64 get_page_table_size(void)
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{
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return 0x14000;
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}
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static unsigned int zynqmp_get_silicon_version_secure(void)
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{
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u32 ver;
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ver = readl(&csu_base->version);
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ver &= ZYNQMP_SILICON_VER_MASK;
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ver >>= ZYNQMP_SILICON_VER_SHIFT;
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return ver;
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}
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unsigned int zynqmp_get_silicon_version(void)
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{
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if (current_el() == 3)
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return zynqmp_get_silicon_version_secure();
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gd->cpu_clk = get_tbclk();
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switch (gd->cpu_clk) {
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case 0 ... 1000000:
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return ZYNQMP_CSU_VERSION_VELOCE;
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case 50000000:
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return ZYNQMP_CSU_VERSION_QEMU;
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case 4000000:
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return ZYNQMP_CSU_VERSION_EP108;
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}
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return ZYNQMP_CSU_VERSION_SILICON;
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}
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