upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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500 lines
17 KiB
500 lines
17 KiB
/*
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* SMSC LAN9[12]1[567] Network driver
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SMC911X_H_
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#define _SMC911X_H_
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#include <linux/types.h>
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#define DRIVERNAME "smc911x"
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#if defined (CONFIG_SMC911X_32_BIT) && \
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defined (CONFIG_SMC911X_16_BIT)
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#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
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CONFIG_SMC911X_16_BIT shall be set"
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#endif
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#if defined (CONFIG_SMC911X_32_BIT)
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static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
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{
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return *(volatile u32*)(dev->iobase + offset);
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}
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u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
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__attribute__((weak, alias("__smc911x_reg_read")));
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static inline void __smc911x_reg_write(struct eth_device *dev,
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u32 offset, u32 val)
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{
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*(volatile u32*)(dev->iobase + offset) = val;
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}
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void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
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__attribute__((weak, alias("__smc911x_reg_write")));
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#elif defined (CONFIG_SMC911X_16_BIT)
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static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
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{
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volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
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return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
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}
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static inline void smc911x_reg_write(struct eth_device *dev,
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u32 offset, u32 val)
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{
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*(volatile u16 *)(dev->iobase + offset) = (u16)val;
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*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
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}
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#else
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#error "SMC911X: undefined bus width"
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#endif /* CONFIG_SMC911X_16_BIT */
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/* Below are the register offsets and bit definitions
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* of the Lan911x memory space
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*/
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#define RX_DATA_FIFO 0x00
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#define TX_DATA_FIFO 0x20
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#define TX_CMD_A_INT_ON_COMP 0x80000000
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#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
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#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
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#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
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#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
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#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
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#define TX_CMD_A_INT_FIRST_SEG 0x00002000
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#define TX_CMD_A_INT_LAST_SEG 0x00001000
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#define TX_CMD_A_BUF_SIZE 0x000007FF
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#define TX_CMD_B_PKT_TAG 0xFFFF0000
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#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
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#define TX_CMD_B_DISABLE_PADDING 0x00001000
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#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
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#define RX_STATUS_FIFO 0x40
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#define RX_STS_PKT_LEN 0x3FFF0000
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#define RX_STS_ES 0x00008000
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#define RX_STS_BCST 0x00002000
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#define RX_STS_LEN_ERR 0x00001000
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#define RX_STS_RUNT_ERR 0x00000800
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#define RX_STS_MCAST 0x00000400
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#define RX_STS_TOO_LONG 0x00000080
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#define RX_STS_COLL 0x00000040
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#define RX_STS_ETH_TYPE 0x00000020
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#define RX_STS_WDOG_TMT 0x00000010
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#define RX_STS_MII_ERR 0x00000008
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#define RX_STS_DRIBBLING 0x00000004
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#define RX_STS_CRC_ERR 0x00000002
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#define RX_STATUS_FIFO_PEEK 0x44
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#define TX_STATUS_FIFO 0x48
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#define TX_STS_TAG 0xFFFF0000
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#define TX_STS_ES 0x00008000
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#define TX_STS_LOC 0x00000800
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#define TX_STS_NO_CARR 0x00000400
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#define TX_STS_LATE_COLL 0x00000200
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#define TX_STS_MANY_COLL 0x00000100
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#define TX_STS_COLL_CNT 0x00000078
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#define TX_STS_MANY_DEFER 0x00000004
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#define TX_STS_UNDERRUN 0x00000002
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#define TX_STS_DEFERRED 0x00000001
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#define TX_STATUS_FIFO_PEEK 0x4C
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#define ID_REV 0x50
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#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
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#define ID_REV_REV_ID 0x0000FFFF /* RO */
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#define INT_CFG 0x54
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#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
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#define INT_CFG_INT_DEAS_CLR 0x00004000
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#define INT_CFG_INT_DEAS_STS 0x00002000
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#define INT_CFG_IRQ_INT 0x00001000 /* RO */
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#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
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/* R/W Not Affected by SW Reset */
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#define INT_CFG_IRQ_POL 0x00000010
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/* R/W Not Affected by SW Reset */
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#define INT_CFG_IRQ_TYPE 0x00000001
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#define INT_STS 0x58
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#define INT_STS_SW_INT 0x80000000 /* R/WC */
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#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
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#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
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#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
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#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
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#define INT_STS_TX_IOC 0x00200000 /* R/WC */
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#define INT_STS_RXD_INT 0x00100000 /* R/WC */
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#define INT_STS_GPT_INT 0x00080000 /* R/WC */
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#define INT_STS_PHY_INT 0x00040000 /* RO */
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#define INT_STS_PME_INT 0x00020000 /* R/WC */
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#define INT_STS_TXSO 0x00010000 /* R/WC */
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#define INT_STS_RWT 0x00008000 /* R/WC */
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#define INT_STS_RXE 0x00004000 /* R/WC */
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#define INT_STS_TXE 0x00002000 /* R/WC */
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/*#define INT_STS_ERX 0x00001000*/ /* R/WC */
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#define INT_STS_TDFU 0x00000800 /* R/WC */
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#define INT_STS_TDFO 0x00000400 /* R/WC */
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#define INT_STS_TDFA 0x00000200 /* R/WC */
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#define INT_STS_TSFF 0x00000100 /* R/WC */
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#define INT_STS_TSFL 0x00000080 /* R/WC */
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/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
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#define INT_STS_RDFO 0x00000040 /* R/WC */
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#define INT_STS_RDFL 0x00000020 /* R/WC */
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#define INT_STS_RSFF 0x00000010 /* R/WC */
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#define INT_STS_RSFL 0x00000008 /* R/WC */
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#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
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#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
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#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
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#define INT_EN 0x5C
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#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
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#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
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#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
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#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
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/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
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#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
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#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
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#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
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#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
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#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
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#define INT_EN_TXSO_EN 0x00010000 /* R/W */
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#define INT_EN_RWT_EN 0x00008000 /* R/W */
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#define INT_EN_RXE_EN 0x00004000 /* R/W */
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#define INT_EN_TXE_EN 0x00002000 /* R/W */
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/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
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#define INT_EN_TDFU_EN 0x00000800 /* R/W */
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#define INT_EN_TDFO_EN 0x00000400 /* R/W */
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#define INT_EN_TDFA_EN 0x00000200 /* R/W */
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#define INT_EN_TSFF_EN 0x00000100 /* R/W */
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#define INT_EN_TSFL_EN 0x00000080 /* R/W */
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/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
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#define INT_EN_RDFO_EN 0x00000040 /* R/W */
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#define INT_EN_RDFL_EN 0x00000020 /* R/W */
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#define INT_EN_RSFF_EN 0x00000010 /* R/W */
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#define INT_EN_RSFL_EN 0x00000008 /* R/W */
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#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
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#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
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#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
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#define BYTE_TEST 0x64
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#define FIFO_INT 0x68
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#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
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#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
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#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
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#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
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#define RX_CFG 0x6C
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#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
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#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
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#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
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#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
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#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
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#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
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#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
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/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
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#define TX_CFG 0x70
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/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
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/* R/W Self Clearing */
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/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
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#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
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#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
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#define TX_CFG_TXSAO 0x00000004 /* R/W */
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#define TX_CFG_TX_ON 0x00000002 /* R/W */
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#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
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#define HW_CFG 0x74
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#define HW_CFG_TTM 0x00200000 /* R/W */
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#define HW_CFG_SF 0x00100000 /* R/W */
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#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
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#define HW_CFG_TR 0x00003000 /* R/W */
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#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
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#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
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#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
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#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
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#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
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#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
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#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
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#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
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#define HW_CFG_SRST_TO 0x00000002 /* RO */
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#define HW_CFG_SRST 0x00000001 /* Self Clearing */
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#define RX_DP_CTRL 0x78
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#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
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#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
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#define RX_FIFO_INF 0x7C
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#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
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#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
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#define TX_FIFO_INF 0x80
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#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
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#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
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#define PMT_CTRL 0x84
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#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
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#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
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#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
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#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
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/* R/W Not Affected by SW Reset */
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#define PMT_CTRL_PME_TYPE 0x00000040
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#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
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#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
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#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
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#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
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#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
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#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
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#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
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/* R/W Not Affected by SW Reset */
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#define PMT_CTRL_PME_EN 0x00000002
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#define PMT_CTRL_READY 0x00000001 /* RO */
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#define GPIO_CFG 0x88
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#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
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#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
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#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
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#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
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#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
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#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
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#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
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#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
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#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
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#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
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#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
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#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
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#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
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#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
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#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
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#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
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#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
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#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
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#define GPT_CFG 0x8C
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#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
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#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
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#define GPT_CNT 0x90
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#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
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#define ENDIAN 0x98
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#define FREE_RUN 0x9C
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#define RX_DROP 0xA0
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#define MAC_CSR_CMD 0xA4
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#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
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#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
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#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
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#define MAC_CSR_DATA 0xA8
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#define AFC_CFG 0xAC
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#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
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#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
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#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
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#define AFC_CFG_FCMULT 0x00000008 /* R/W */
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#define AFC_CFG_FCBRD 0x00000004 /* R/W */
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#define AFC_CFG_FCADD 0x00000002 /* R/W */
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#define AFC_CFG_FCANY 0x00000001 /* R/W */
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#define E2P_CMD 0xB0
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#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
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#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
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#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
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#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
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#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
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#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
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#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
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#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
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#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
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#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
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#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
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#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
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#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
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#define E2P_DATA 0xB4
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#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
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/* end of LAN register offsets and bit definitions */
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/* MAC Control and Status registers */
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#define MAC_CR 0x01 /* R/W */
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/* MAC_CR - MAC Control Register */
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#define MAC_CR_RXALL 0x80000000
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/* TODO: delete this bit? It is not described in the data sheet. */
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#define MAC_CR_HBDIS 0x10000000
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#define MAC_CR_RCVOWN 0x00800000
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#define MAC_CR_LOOPBK 0x00200000
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#define MAC_CR_FDPX 0x00100000
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#define MAC_CR_MCPAS 0x00080000
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#define MAC_CR_PRMS 0x00040000
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#define MAC_CR_INVFILT 0x00020000
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#define MAC_CR_PASSBAD 0x00010000
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#define MAC_CR_HFILT 0x00008000
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#define MAC_CR_HPFILT 0x00002000
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#define MAC_CR_LCOLL 0x00001000
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#define MAC_CR_BCAST 0x00000800
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#define MAC_CR_DISRTY 0x00000400
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#define MAC_CR_PADSTR 0x00000100
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#define MAC_CR_BOLMT_MASK 0x000000C0
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#define MAC_CR_DFCHK 0x00000020
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#define MAC_CR_TXEN 0x00000008
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#define MAC_CR_RXEN 0x00000004
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#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
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#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
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#define HASHH 0x04 /* R/W */
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#define HASHL 0x05 /* R/W */
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#define MII_ACC 0x06 /* R/W */
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#define MII_ACC_PHY_ADDR 0x0000F800
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#define MII_ACC_MIIRINDA 0x000007C0
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#define MII_ACC_MII_WRITE 0x00000002
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#define MII_ACC_MII_BUSY 0x00000001
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#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
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#define FLOW 0x08 /* R/W */
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#define FLOW_FCPT 0xFFFF0000
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#define FLOW_FCPASS 0x00000004
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#define FLOW_FCEN 0x00000002
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#define FLOW_FCBSY 0x00000001
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#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
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#define VLAN1_VTI1 0x0000ffff
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#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
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#define VLAN2_VTI2 0x0000ffff
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#define WUFF 0x0B /* WO */
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#define WUCSR 0x0C /* R/W */
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#define WUCSR_GUE 0x00000200
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#define WUCSR_WUFR 0x00000040
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#define WUCSR_MPR 0x00000020
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#define WUCSR_WAKE_EN 0x00000004
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#define WUCSR_MPEN 0x00000002
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/* Chip ID values */
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#define CHIP_89218 0x218a
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#define CHIP_9115 0x115
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#define CHIP_9116 0x116
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#define CHIP_9117 0x117
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#define CHIP_9118 0x118
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#define CHIP_9211 0x9211
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#define CHIP_9215 0x115a
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#define CHIP_9216 0x116a
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#define CHIP_9217 0x117a
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#define CHIP_9218 0x118a
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#define CHIP_9220 0x9220
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#define CHIP_9221 0x9221
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struct chip_id {
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u16 id;
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char *name;
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};
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static const struct chip_id chip_ids[] = {
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{ CHIP_89218, "LAN89218" },
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{ CHIP_9115, "LAN9115" },
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{ CHIP_9116, "LAN9116" },
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{ CHIP_9117, "LAN9117" },
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{ CHIP_9118, "LAN9118" },
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{ CHIP_9211, "LAN9211" },
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{ CHIP_9215, "LAN9215" },
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{ CHIP_9216, "LAN9216" },
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{ CHIP_9217, "LAN9217" },
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{ CHIP_9218, "LAN9218" },
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{ CHIP_9220, "LAN9220" },
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{ CHIP_9221, "LAN9221" },
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{ 0, NULL },
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};
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static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
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{
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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smc911x_reg_write(dev, MAC_CSR_CMD,
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MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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return smc911x_reg_read(dev, MAC_CSR_DATA);
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}
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static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
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{
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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smc911x_reg_write(dev, MAC_CSR_DATA, data);
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smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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}
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static int smc911x_detect_chip(struct eth_device *dev)
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{
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unsigned long val, i;
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val = smc911x_reg_read(dev, BYTE_TEST);
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if (val == 0xffffffff) {
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/* Special case -- no chip present */
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return -1;
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} else if (val != 0x87654321) {
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printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
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return -1;
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}
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val = smc911x_reg_read(dev, ID_REV) >> 16;
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for (i = 0; chip_ids[i].id != 0; i++) {
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if (chip_ids[i].id == val) break;
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}
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if (!chip_ids[i].id) {
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printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
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return -1;
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}
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dev->priv = (void *)&chip_ids[i];
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return 0;
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}
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static void smc911x_reset(struct eth_device *dev)
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{
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int timeout;
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/*
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* Take out of PM setting first
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* Device is already wake up if PMT_CTRL_READY bit is set
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*/
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if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
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/* Write to the bytetest will take out of powerdown */
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smc911x_reg_write(dev, BYTE_TEST, 0x0);
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timeout = 10;
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while (timeout-- &&
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!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
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udelay(10);
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if (timeout < 0) {
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printf(DRIVERNAME
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|
": timeout waiting for PM restore\n");
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return;
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}
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}
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/* Disable interrupts */
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smc911x_reg_write(dev, INT_EN, 0);
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smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
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timeout = 1000;
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while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
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udelay(10);
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if (timeout < 0) {
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printf(DRIVERNAME ": reset timeout\n");
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return;
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}
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/* Reset the FIFO level and flow control settings */
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smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
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smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
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/* Set to LED outputs */
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smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
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}
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#endif
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