upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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64 lines
1.8 KiB
64 lines
1.8 KiB
Intel LPC Device Binding
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========================
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The device tree node which describes the operation of the Intel Low Pin
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Count device is as follows:
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Required properties :
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- compatible = "intel,lpc"
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- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
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ALT_GP_SMI_EN register
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- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
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cell pairs can be provided - the first of each pair is the base address and
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the second is the size. These are written into the GENx_DEC registers of
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the LPC device
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- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
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values are:
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0 No effect (default)
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1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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2 SCI (if corresponding GPIO_EN bit is also set)
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- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
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one cell for each.
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0x00 - 0000 = Reserved
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0x01 - 0001 = Reserved
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0x02 - 0010 = Reserved
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0x03 - 0011 = IRQ3
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0x04 - 0100 = IRQ4
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0x05 - 0101 = IRQ5
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0x06 - 0110 = IRQ6
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0x07 - 0111 = IRQ7
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0x08 - 1000 = Reserved
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0x09 - 1001 = IRQ9
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0x0A - 1010 = IRQ10
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0x0B - 1011 = IRQ11
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0x0C - 1100 = IRQ12
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0x0D - 1101 = Reserved
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0x0E - 1110 = IRQ14
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0x0F - 1111 = IRQ15
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PIRQ[n]_ROUT[7] - PIRQ Routing Control
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0x80 - The PIRQ is not routed.
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Example
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-------
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lpc {
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compatible = "intel,lpc";
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#address-cells = <1>;
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#size-cells = <1>;
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intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
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intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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0x80 0x80 0x80 0x80>;
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/*
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* GPI routing
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* 0 No effect (default)
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* 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is
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* also set)
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* 2 SCI (if corresponding GPIO_EN bit is also set)
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*/
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intel,gpi-routing = <0 0 0 0 0 0 0 2
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1 0 0 0 0 0 0 0>;
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/* Enable EC SMI source */
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intel,alt-gp-smi-enable = <0x0100>;
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};
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