upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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73 lines
1.4 KiB
73 lines
1.4 KiB
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <fsl_csu.h>
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#include <asm/arch/ns_access.h>
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#include <asm/arch/fsl_serdes.h>
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void set_devices_ns_access(unsigned long index, u16 val)
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{
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u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
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u32 *reg;
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uint32_t tmp;
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reg = base + index / 2;
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tmp = in_be32(reg);
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if (index % 2 == 0) {
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tmp &= 0x0000ffff;
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tmp |= val << 16;
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} else {
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tmp &= 0xffff0000;
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tmp |= val;
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}
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out_be32(reg, tmp);
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}
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static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
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{
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int i;
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for (i = 0; i < num; i++)
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set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
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}
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void enable_layerscape_ns_access(void)
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{
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#ifdef CONFIG_ARM64
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if (current_el() == 3)
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#endif
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enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
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}
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void set_pcie_ns_access(int pcie, u16 val)
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{
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switch (pcie) {
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#ifdef CONFIG_PCIE1
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case PCIE1:
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set_devices_ns_access(CSU_CSLX_PCIE1, val);
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set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
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return;
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#endif
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#ifdef CONFIG_PCIE2
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case PCIE2:
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set_devices_ns_access(CSU_CSLX_PCIE2, val);
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set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
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return;
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#endif
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#ifdef CONFIG_PCIE3
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case PCIE3:
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set_devices_ns_access(CSU_CSLX_PCIE3, val);
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set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
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return;
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#endif
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default:
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debug("The PCIE%d doesn't exist!\n", pcie);
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return;
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}
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}
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