upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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55 lines
1.1 KiB
55 lines
1.1 KiB
/*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <pch.h>
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#define BIOS_CTRL 0xd8
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static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
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{
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u32 rcba;
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dm_pci_read_config32(dev, PCH_RCBA, &rcba);
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
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rcba = rcba & 0xffffc000;
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*sbasep = rcba + 0x3020;
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return 0;
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}
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static int pch7_set_spi_protect(struct udevice *dev, bool protect)
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{
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uint8_t bios_cntl;
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/* Adjust the BIOS write protect to dis/allow write commands */
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dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
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if (protect)
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bios_cntl &= ~BIOS_CTRL_BIOSWE;
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else
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bios_cntl |= BIOS_CTRL_BIOSWE;
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dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
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return 0;
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}
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static const struct pch_ops pch7_ops = {
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.get_sbase = pch7_get_sbase,
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.set_spi_protect = pch7_set_spi_protect,
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};
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static const struct udevice_id pch7_ids[] = {
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{ .compatible = "intel,pch7" },
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{ }
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};
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U_BOOT_DRIVER(pch7_drv) = {
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.name = "intel-pch7",
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.id = UCLASS_PCH,
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.of_match = pch7_ids,
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.ops = &pch7_ops,
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};
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