upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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70 lines
1.7 KiB
70 lines
1.7 KiB
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_validate.h>
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#include <fsl_sfp.h>
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#ifdef CONFIG_LS102XA
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#include <asm/arch/immap_ls102xa.h>
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#endif
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#if defined(CONFIG_MPC85xx)
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#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#else
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#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
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#endif
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#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
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#define gur_in32(a) in_le32(a)
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#else
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#define gur_in32(a) in_be32(a)
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#endif
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/* Check the Boot Mode. If Secure, return 1 else return 0 */
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int fsl_check_boot_mode_secure(void)
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{
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uint32_t val;
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struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
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val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
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if (val == ITS_MASK)
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return 1;
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#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
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/* For PBL based platforms check the SB_EN bit in RCWSR */
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val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
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if (val == RCW_SB_EN_MASK)
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return 1;
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#endif
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#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
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/* For Non-PBL Platforms, check the Device Status register 2*/
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val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
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if (val != MPC85xx_PORDEVSR2_SBC_MASK)
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return 1;
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#endif
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return 0;
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}
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int fsl_setenv_chain_of_trust(void)
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{
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/* Check Boot Mode
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* If Boot Mode is Non-Secure, no changes are required
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*/
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if (fsl_check_boot_mode_secure() == 0)
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return 0;
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/* If Boot mode is Secure, set the environment variables
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* bootdelay = 0 (To disable Boot Prompt)
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* bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
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*/
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setenv("bootdelay", "0");
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setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
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return 0;
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}
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