upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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55 lines
1.6 KiB
55 lines
1.6 KiB
/*
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* clocks_am33xx.h
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*
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* AM33xx clock define
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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#define OSC (V_OSCK/1000000)
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/* MAIN PLL Fdll = 550 MHZ, */
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#define MPUPLL_M 550
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#define MPUPLL_N (OSC-1)
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#define MPUPLL_M2 1
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/* Core PLL Fdll = 1 GHZ, */
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#define COREPLL_M 1000
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#define COREPLL_N (OSC-1)
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#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
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#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
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#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
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/*
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* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
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* frequency needs to be set to 960 MHZ. Hence,
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* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
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*/
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#define PERPLL_M 960
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#define PERPLL_N (OSC-1)
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#define PERPLL_M2 5
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/* DDR Freq is 266 MHZ for now */
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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#define DDRPLL_M 266
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#define DDRPLL_N (OSC-1)
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#define DDRPLL_M2 1
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extern void pll_init(void);
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extern void enable_emif_clocks(void);
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#endif /* endif _CLOCKS_AM33XX_H_ */
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