upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
2.0 KiB
54 lines
2.0 KiB
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _PANTHEON_H
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#define _PANTHEON_H
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
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#define APBC_RST (1<<2) /* Reset Generation */
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/* Functional Clock Selection Mask */
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#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
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/* Common APMU register bit definitions */
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#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
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#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
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#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
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#define APMU_AXI_RST (1<<0) /* AXI Reset */
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/* Register Base Addresses */
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#define PANTHEON_DRAM_BASE 0xB0000000
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#define PANTHEON_TIMER_BASE 0xD4014000
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#define PANTHEON_WD_TIMER_BASE 0xD4080000
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#define PANTHEON_APBC_BASE 0xD4015000
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#define PANTHEON_UART1_BASE 0xD4017000
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#define PANTHEON_UART2_BASE 0xD4018000
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#define PANTHEON_GPIO_BASE 0xD4019000
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#define PANTHEON_MFPR_BASE 0xD401E000
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#define PANTHEON_MPMU_BASE 0xD4050000
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#define PANTHEON_APMU_BASE 0xD4282800
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#define PANTHEON_CPU_BASE 0xD4282C00
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#endif /* _PANTHEON_H */
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