upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
3.1 KiB
116 lines
3.1 KiB
/*
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* (C) Copyright 2003-2009
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_UC101 1 /* UC101 board */
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#define CONFIG_HOSTNAME uc101
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#include "manroland/common.h"
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#include "manroland/mpc5200-common.h"
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/*
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* Serial console configuration
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*/
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_MAX_FLASH_SECT 140
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_SECT_SIZE 0x10000
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/*
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* Memory map
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*/
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#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */
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#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */
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/* SRAM */
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#define SRAM_BASE CONFIG_SYS_SRAM_BASE
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#define SRAM_LEN 0x1fffff
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#define SRAM_END (SRAM_BASE + SRAM_LEN)
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/*
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* GPIO configuration
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044
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#define CONFIG_SYS_MEMTEST_START 0x00300000
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#define CONFIG_SYS_MEMTEST_END 0x00f00000
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#define CONFIG_SYS_LOAD_ADDR 0x300000
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#define CONFIG_SYS_BOOTCS_CFG 0x00045D00
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/* 8Mbit SRAM @0x80100000 */
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#define CONFIG_SYS_CS1_SIZE 0x00200000
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#define CONFIG_SYS_CS1_CFG 0x21D00
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/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
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#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE
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#define CONFIG_SYS_CS3_SIZE 0x00000100
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#define CONFIG_SYS_CS3_CFG 0x00081802
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/* Interbus Master 16 Bit */
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#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER
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#define CONFIG_SYS_CS6_SIZE 0x00010000
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#define CONFIG_SYS_CS6_CFG 0x00FF3500
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/* Interbus EPLD 8 Bit */
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#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD
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#define CONFIG_SYS_CS7_SIZE 0x00010000
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#define CONFIG_SYS_CS7_CFG 0x00081800
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/
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/*---------------------------------------------------------------------*/
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/* Display addresses */
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/*---------------------------------------------------------------------*/
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#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
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#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
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#endif /* __CONFIG_H */
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