upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
1.5 KiB
78 lines
1.5 KiB
/*
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* Port Masks
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*/
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#ifndef __BFIN_PERIPHERAL_PORT__
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#define __BFIN_PERIPHERAL_PORT__
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/* PORT_MUX Masks */
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#define PJSE 0x0001
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#define PJCE_MASK 0x0006
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#define PJCE_SPORT 0x0000
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#define PJCE_CAN 0x0001
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#define PJCE_SPI 0x0002
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#define PFDE 0x0008
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#define PFTE 0x0010
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#define PFS6E 0x0020
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#define PFS5E 0x0040
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#define PFS4E 0x0080
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#define PFFE 0x0100
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#define PGSE 0x0200
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#define PGRE 0x0400
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#define PGTE 0x0800
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/* Port F Masks */
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#define PF0 0x0001
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#define PF1 0x0002
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#define PF2 0x0004
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#define PF3 0x0008
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#define PF4 0x0010
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#define PF5 0x0020
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#define PF6 0x0040
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#define PF7 0x0080
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#define PF8 0x0100
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#define PF9 0x0200
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#define PF10 0x0400
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#define PF11 0x0800
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#define PF12 0x1000
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#define PF13 0x2000
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#define PF14 0x4000
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#define PF15 0x8000
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/* Port G Masks */
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#define PG0 0x0001
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#define PG1 0x0002
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#define PG2 0x0004
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#define PG3 0x0008
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#define PG4 0x0010
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#define PG5 0x0020
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#define PG6 0x0040
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#define PG7 0x0080
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#define PG8 0x0100
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#define PG9 0x0200
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#define PG10 0x0400
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#define PG11 0x0800
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#define PG12 0x1000
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#define PG13 0x2000
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#define PG14 0x4000
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#define PG15 0x8000
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/* Port H Masks */
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#define PH0 0x0001
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#define PH1 0x0002
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#define PH2 0x0004
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#define PH3 0x0008
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#define PH4 0x0010
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#define PH5 0x0020
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#define PH6 0x0040
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#define PH7 0x0080
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#define PH8 0x0100
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#define PH9 0x0200
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#define PH10 0x0400
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#define PH11 0x0800
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#define PH12 0x1000
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#define PH13 0x2000
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#define PH14 0x4000
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#define PH15 0x8000
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#endif
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