upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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817 lines
24 KiB
817 lines
24 KiB
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of the Altera Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <wait_bit.h>
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#include <spi.h>
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#include <bouncebuf.h>
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#include "cadence_qspi.h"
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#define CQSPI_REG_POLL_US 1 /* 1us */
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#define CQSPI_REG_RETRY 10000
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#define CQSPI_POLL_IDLE_RETRY 3
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#define CQSPI_FIFO_WIDTH 4
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#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
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/* Transfer mode */
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#define CQSPI_INST_TYPE_SINGLE 0
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#define CQSPI_INST_TYPE_DUAL 1
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#define CQSPI_INST_TYPE_QUAD 2
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#define CQSPI_STIG_DATA_LEN_MAX 8
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#define CQSPI_DUMMY_CLKS_PER_BYTE 8
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#define CQSPI_DUMMY_BYTES_MAX 4
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#define CQSPI_REG_SRAM_FILL_THRESHOLD \
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((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
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/****************************************************************************
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* Controller's configuration and status register (offset from QSPI_BASE)
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****************************************************************************/
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#define CQSPI_REG_CONFIG 0x00
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#define CQSPI_REG_CONFIG_ENABLE BIT(0)
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#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
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#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
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#define CQSPI_REG_CONFIG_DIRECT BIT(7)
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#define CQSPI_REG_CONFIG_DECODE BIT(9)
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#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
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#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
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#define CQSPI_REG_CONFIG_BAUD_LSB 19
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#define CQSPI_REG_CONFIG_IDLE_LSB 31
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#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
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#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
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#define CQSPI_REG_RD_INSTR 0x04
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#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
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#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
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#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
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#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
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#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
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#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
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#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
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#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
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#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
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#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
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#define CQSPI_REG_WR_INSTR 0x08
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#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
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#define CQSPI_REG_DELAY 0x0C
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#define CQSPI_REG_DELAY_TSLCH_LSB 0
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#define CQSPI_REG_DELAY_TCHSH_LSB 8
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#define CQSPI_REG_DELAY_TSD2D_LSB 16
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#define CQSPI_REG_DELAY_TSHSL_LSB 24
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#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
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#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
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#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
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#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
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#define CQSPI_REG_RD_DATA_CAPTURE 0x10
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#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
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#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
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#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
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#define CQSPI_REG_SIZE 0x14
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#define CQSPI_REG_SIZE_ADDRESS_LSB 0
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#define CQSPI_REG_SIZE_PAGE_LSB 4
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#define CQSPI_REG_SIZE_BLOCK_LSB 16
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#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
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#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
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#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
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#define CQSPI_REG_SRAMPARTITION 0x18
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#define CQSPI_REG_INDIRECTTRIGGER 0x1C
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#define CQSPI_REG_REMAP 0x24
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#define CQSPI_REG_MODE_BIT 0x28
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#define CQSPI_REG_SDRAMLEVEL 0x2C
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#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
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#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
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#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
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#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
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#define CQSPI_REG_IRQSTATUS 0x40
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#define CQSPI_REG_IRQMASK 0x44
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#define CQSPI_REG_INDIRECTRD 0x60
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#define CQSPI_REG_INDIRECTRD_START BIT(0)
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#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
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#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
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#define CQSPI_REG_INDIRECTRD_DONE BIT(5)
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#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
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#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
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#define CQSPI_REG_INDIRECTRDBYTES 0x6C
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#define CQSPI_REG_CMDCTRL 0x90
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#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
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#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
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#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
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#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
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#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
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#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
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#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
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#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
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#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
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#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
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#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
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#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
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#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
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#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
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#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
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#define CQSPI_REG_INDIRECTWR 0x70
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#define CQSPI_REG_INDIRECTWR_START BIT(0)
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#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
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#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
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#define CQSPI_REG_INDIRECTWR_DONE BIT(5)
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#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
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#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
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#define CQSPI_REG_INDIRECTWRBYTES 0x7C
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#define CQSPI_REG_CMDADDRESS 0x94
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#define CQSPI_REG_CMDREADDATALOWER 0xA0
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#define CQSPI_REG_CMDREADDATAUPPER 0xA4
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#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
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#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
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#define CQSPI_REG_IS_IDLE(base) \
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((readl(base + CQSPI_REG_CONFIG) >> \
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CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
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#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
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(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
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CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
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#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
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(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
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CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
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static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
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unsigned int addr_width)
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{
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unsigned int addr;
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addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
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if (addr_width == 4)
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addr = (addr << 8) | addr_buf[3];
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return addr;
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}
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void cadence_qspi_apb_controller_enable(void *reg_base)
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{
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unsigned int reg;
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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reg |= CQSPI_REG_CONFIG_ENABLE;
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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}
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void cadence_qspi_apb_controller_disable(void *reg_base)
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{
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unsigned int reg;
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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reg &= ~CQSPI_REG_CONFIG_ENABLE;
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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}
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/* Return 1 if idle, otherwise return 0 (busy). */
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static unsigned int cadence_qspi_wait_idle(void *reg_base)
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{
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unsigned int start, count = 0;
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/* timeout in unit of ms */
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unsigned int timeout = 5000;
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start = get_timer(0);
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for ( ; get_timer(start) < timeout ; ) {
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if (CQSPI_REG_IS_IDLE(reg_base))
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count++;
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else
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count = 0;
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/*
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* Ensure the QSPI controller is in true idle state after
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* reading back the same idle status consecutively
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*/
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if (count >= CQSPI_POLL_IDLE_RETRY)
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return 1;
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}
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/* Timeout, still in busy mode. */
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printf("QSPI: QSPI is still busy after poll for %d times.\n",
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CQSPI_REG_RETRY);
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return 0;
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}
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void cadence_qspi_apb_readdata_capture(void *reg_base,
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unsigned int bypass, unsigned int delay)
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{
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unsigned int reg;
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cadence_qspi_apb_controller_disable(reg_base);
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reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
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if (bypass)
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reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
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else
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reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
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reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
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<< CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
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reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
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<< CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
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writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
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cadence_qspi_apb_controller_enable(reg_base);
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}
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void cadence_qspi_apb_config_baudrate_div(void *reg_base,
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unsigned int ref_clk_hz, unsigned int sclk_hz)
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{
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unsigned int reg;
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unsigned int div;
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cadence_qspi_apb_controller_disable(reg_base);
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
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/*
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* The baud_div field in the config reg is 4 bits, and the ref clock is
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* divided by 2 * (baud_div + 1). Round up the divider to ensure the
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* SPI clock rate is less than or equal to the requested clock rate.
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*/
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div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
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/* ensure the baud rate doesn't exceed the max value */
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if (div > CQSPI_REG_CONFIG_BAUD_MASK)
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div = CQSPI_REG_CONFIG_BAUD_MASK;
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debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
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ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
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reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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cadence_qspi_apb_controller_enable(reg_base);
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}
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void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
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{
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unsigned int reg;
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cadence_qspi_apb_controller_disable(reg_base);
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
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if (mode & SPI_CPOL)
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reg |= CQSPI_REG_CONFIG_CLK_POL;
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if (mode & SPI_CPHA)
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reg |= CQSPI_REG_CONFIG_CLK_PHA;
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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cadence_qspi_apb_controller_enable(reg_base);
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}
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void cadence_qspi_apb_chipselect(void *reg_base,
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unsigned int chip_select, unsigned int decoder_enable)
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{
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unsigned int reg;
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cadence_qspi_apb_controller_disable(reg_base);
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debug("%s : chipselect %d decode %d\n", __func__, chip_select,
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decoder_enable);
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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/* docoder */
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if (decoder_enable) {
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reg |= CQSPI_REG_CONFIG_DECODE;
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} else {
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reg &= ~CQSPI_REG_CONFIG_DECODE;
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/* Convert CS if without decoder.
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* CS0 to 4b'1110
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* CS1 to 4b'1101
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* CS2 to 4b'1011
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* CS3 to 4b'0111
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*/
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chip_select = 0xF & ~(1 << chip_select);
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}
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reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
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<< CQSPI_REG_CONFIG_CHIPSELECT_LSB);
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reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
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<< CQSPI_REG_CONFIG_CHIPSELECT_LSB;
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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cadence_qspi_apb_controller_enable(reg_base);
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}
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void cadence_qspi_apb_delay(void *reg_base,
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unsigned int ref_clk, unsigned int sclk_hz,
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unsigned int tshsl_ns, unsigned int tsd2d_ns,
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unsigned int tchsh_ns, unsigned int tslch_ns)
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{
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unsigned int ref_clk_ns;
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unsigned int sclk_ns;
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unsigned int tshsl, tchsh, tslch, tsd2d;
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unsigned int reg;
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cadence_qspi_apb_controller_disable(reg_base);
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/* Convert to ns. */
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ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
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/* Convert to ns. */
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sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
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/* The controller adds additional delay to that programmed in the reg */
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if (tshsl_ns >= sclk_ns + ref_clk_ns)
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tshsl_ns -= sclk_ns + ref_clk_ns;
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if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
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tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
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tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
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tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
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tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
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tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
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reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
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<< CQSPI_REG_DELAY_TSHSL_LSB);
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reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
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<< CQSPI_REG_DELAY_TCHSH_LSB);
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reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
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<< CQSPI_REG_DELAY_TSLCH_LSB);
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reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
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<< CQSPI_REG_DELAY_TSD2D_LSB);
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writel(reg, reg_base + CQSPI_REG_DELAY);
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cadence_qspi_apb_controller_enable(reg_base);
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}
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void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
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{
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unsigned reg;
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cadence_qspi_apb_controller_disable(plat->regbase);
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/* Configure the device size and address bytes */
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reg = readl(plat->regbase + CQSPI_REG_SIZE);
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/* Clear the previous value */
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reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
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reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
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reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
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reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
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writel(reg, plat->regbase + CQSPI_REG_SIZE);
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/* Configure the remap address register, no remap */
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writel(0, plat->regbase + CQSPI_REG_REMAP);
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/* Indirect mode configurations */
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writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
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/* Disable all interrupts */
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writel(0, plat->regbase + CQSPI_REG_IRQMASK);
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cadence_qspi_apb_controller_enable(plat->regbase);
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}
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static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
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unsigned int reg)
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{
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unsigned int retry = CQSPI_REG_RETRY;
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/* Write the CMDCTRL without start execution. */
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writel(reg, reg_base + CQSPI_REG_CMDCTRL);
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/* Start execute */
|
|
reg |= CQSPI_REG_CMDCTRL_EXECUTE;
|
|
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
|
|
|
|
while (retry--) {
|
|
reg = readl(reg_base + CQSPI_REG_CMDCTRL);
|
|
if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
if (!retry) {
|
|
printf("QSPI: flash command execution timeout\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* Polling QSPI idle status. */
|
|
if (!cadence_qspi_wait_idle(reg_base))
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* For command RDID, RDSR. */
|
|
int cadence_qspi_apb_command_read(void *reg_base,
|
|
unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
|
|
u8 *rxbuf)
|
|
{
|
|
unsigned int reg;
|
|
unsigned int read_len;
|
|
int status;
|
|
|
|
if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
|
|
printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
|
|
cmdlen, rxlen);
|
|
return -EINVAL;
|
|
}
|
|
|
|
reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
|
|
|
|
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
|
|
|
|
/* 0 means 1 byte. */
|
|
reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
|
|
<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
|
|
status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
|
|
if (status != 0)
|
|
return status;
|
|
|
|
reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
|
|
|
|
/* Put the read value into rx_buf */
|
|
read_len = (rxlen > 4) ? 4 : rxlen;
|
|
memcpy(rxbuf, ®, read_len);
|
|
rxbuf += read_len;
|
|
|
|
if (rxlen > 4) {
|
|
reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
|
|
|
|
read_len = rxlen - read_len;
|
|
memcpy(rxbuf, ®, read_len);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
|
|
int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
|
|
const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
|
|
{
|
|
unsigned int reg = 0;
|
|
unsigned int addr_value;
|
|
unsigned int wr_data;
|
|
unsigned int wr_len;
|
|
|
|
if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
|
|
printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
|
|
cmdlen, txlen);
|
|
return -EINVAL;
|
|
}
|
|
|
|
reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
|
|
|
|
if (cmdlen == 4 || cmdlen == 5) {
|
|
/* Command with address */
|
|
reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
|
|
/* Number of bytes to write. */
|
|
reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
|
|
<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
|
|
/* Get address */
|
|
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
|
|
cmdlen >= 5 ? 4 : 3);
|
|
|
|
writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
|
|
}
|
|
|
|
if (txlen) {
|
|
/* writing data = yes */
|
|
reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
|
|
reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
|
|
<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
|
|
|
|
wr_len = txlen > 4 ? 4 : txlen;
|
|
memcpy(&wr_data, txbuf, wr_len);
|
|
writel(wr_data, reg_base +
|
|
CQSPI_REG_CMDWRITEDATALOWER);
|
|
|
|
if (txlen > 4) {
|
|
txbuf += wr_len;
|
|
wr_len = txlen - wr_len;
|
|
memcpy(&wr_data, txbuf, wr_len);
|
|
writel(wr_data, reg_base +
|
|
CQSPI_REG_CMDWRITEDATAUPPER);
|
|
}
|
|
}
|
|
|
|
/* Execute the command */
|
|
return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
|
|
}
|
|
|
|
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
|
|
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
|
|
unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
|
|
{
|
|
unsigned int reg;
|
|
unsigned int rd_reg;
|
|
unsigned int addr_value;
|
|
unsigned int dummy_clk;
|
|
unsigned int dummy_bytes;
|
|
unsigned int addr_bytes;
|
|
|
|
/*
|
|
* Identify addr_byte. All NOR flash device drivers are using fast read
|
|
* which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
|
|
* With that, the length is in value of 5 or 6. Only FRAM chip from
|
|
* ramtron using normal read (which won't need dummy byte).
|
|
* Unlikely NOR flash using normal read due to performance issue.
|
|
*/
|
|
if (cmdlen >= 5)
|
|
/* to cater fast read where cmd + addr + dummy */
|
|
addr_bytes = cmdlen - 2;
|
|
else
|
|
/* for normal read (only ramtron as of now) */
|
|
addr_bytes = cmdlen - 1;
|
|
|
|
/* Setup the indirect trigger address */
|
|
writel((u32)plat->ahbbase,
|
|
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
|
|
|
|
/* Configure the opcode */
|
|
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
|
|
|
|
if (rx_width & SPI_RX_QUAD)
|
|
/* Instruction and address at DQ0, data at DQ0-3. */
|
|
rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
|
|
|
|
/* Get address */
|
|
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
|
|
writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
|
|
|
|
/* The remaining lenght is dummy bytes. */
|
|
dummy_bytes = cmdlen - addr_bytes - 1;
|
|
if (dummy_bytes) {
|
|
if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
|
|
dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
|
|
|
|
rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
|
|
#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
|
|
writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
|
|
#else
|
|
writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
|
|
#endif
|
|
|
|
/* Convert to clock cycles. */
|
|
dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
|
|
/* Need to minus the mode byte (8 clocks). */
|
|
dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
|
|
|
|
if (dummy_clk)
|
|
rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
|
|
<< CQSPI_REG_RD_INSTR_DUMMY_LSB;
|
|
}
|
|
|
|
writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
|
|
|
|
/* set device size */
|
|
reg = readl(plat->regbase + CQSPI_REG_SIZE);
|
|
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
|
|
reg |= (addr_bytes - 1);
|
|
writel(reg, plat->regbase + CQSPI_REG_SIZE);
|
|
return 0;
|
|
}
|
|
|
|
static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
|
|
{
|
|
u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
|
|
reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
|
|
return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
|
|
}
|
|
|
|
static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
|
|
{
|
|
unsigned int timeout = 10000;
|
|
u32 reg;
|
|
|
|
while (timeout--) {
|
|
reg = cadence_qspi_get_rd_sram_level(plat);
|
|
if (reg)
|
|
return reg;
|
|
udelay(1);
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
|
|
unsigned int n_rx, u8 *rxbuf)
|
|
{
|
|
unsigned int remaining = n_rx;
|
|
unsigned int bytes_to_read = 0;
|
|
struct bounce_buffer bb;
|
|
u8 *bb_rxbuf;
|
|
int ret;
|
|
|
|
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
|
|
|
|
/* Start the indirect read transfer */
|
|
writel(CQSPI_REG_INDIRECTRD_START,
|
|
plat->regbase + CQSPI_REG_INDIRECTRD);
|
|
|
|
ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
|
|
if (ret)
|
|
return ret;
|
|
bb_rxbuf = bb.bounce_buffer;
|
|
|
|
while (remaining > 0) {
|
|
ret = cadence_qspi_wait_for_data(plat);
|
|
if (ret < 0) {
|
|
printf("Indirect write timed out (%i)\n", ret);
|
|
goto failrd;
|
|
}
|
|
|
|
bytes_to_read = ret;
|
|
|
|
while (bytes_to_read != 0) {
|
|
bytes_to_read *= CQSPI_FIFO_WIDTH;
|
|
bytes_to_read = bytes_to_read > remaining ?
|
|
remaining : bytes_to_read;
|
|
readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
|
|
if (bytes_to_read % 4)
|
|
readsb(plat->ahbbase,
|
|
bb_rxbuf + rounddown(bytes_to_read, 4),
|
|
bytes_to_read % 4);
|
|
|
|
bb_rxbuf += bytes_to_read;
|
|
remaining -= bytes_to_read;
|
|
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
|
|
}
|
|
}
|
|
|
|
/* Check indirect done status */
|
|
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
|
|
CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
|
|
if (ret) {
|
|
printf("Indirect read completion error (%i)\n", ret);
|
|
goto failrd;
|
|
}
|
|
|
|
/* Clear indirect completion status */
|
|
writel(CQSPI_REG_INDIRECTRD_DONE,
|
|
plat->regbase + CQSPI_REG_INDIRECTRD);
|
|
bounce_buffer_stop(&bb);
|
|
|
|
return 0;
|
|
|
|
failrd:
|
|
/* Cancel the indirect read */
|
|
writel(CQSPI_REG_INDIRECTRD_CANCEL,
|
|
plat->regbase + CQSPI_REG_INDIRECTRD);
|
|
bounce_buffer_stop(&bb);
|
|
return ret;
|
|
}
|
|
|
|
/* Opcode + Address (3/4 bytes) */
|
|
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
|
|
unsigned int cmdlen, const u8 *cmdbuf)
|
|
{
|
|
unsigned int reg;
|
|
unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
|
|
|
|
if (cmdlen < 4 || cmdbuf == NULL) {
|
|
printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
|
|
cmdlen, (unsigned int)cmdbuf);
|
|
return -EINVAL;
|
|
}
|
|
/* Setup the indirect trigger address */
|
|
writel((u32)plat->ahbbase,
|
|
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
|
|
|
|
/* Configure the opcode */
|
|
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
|
|
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
|
|
|
|
/* Setup write address. */
|
|
reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
|
|
writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
|
|
|
|
reg = readl(plat->regbase + CQSPI_REG_SIZE);
|
|
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
|
|
reg |= (addr_bytes - 1);
|
|
writel(reg, plat->regbase + CQSPI_REG_SIZE);
|
|
return 0;
|
|
}
|
|
|
|
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
|
|
unsigned int n_tx, const u8 *txbuf)
|
|
{
|
|
unsigned int page_size = plat->page_size;
|
|
unsigned int remaining = n_tx;
|
|
unsigned int write_bytes;
|
|
int ret;
|
|
struct bounce_buffer bb;
|
|
u8 *bb_txbuf;
|
|
|
|
/*
|
|
* Handle non-4-byte aligned accesses via bounce buffer to
|
|
* avoid data abort.
|
|
*/
|
|
ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
|
|
if (ret)
|
|
return ret;
|
|
bb_txbuf = bb.bounce_buffer;
|
|
|
|
/* Configure the indirect read transfer bytes */
|
|
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
|
|
|
|
/* Start the indirect write transfer */
|
|
writel(CQSPI_REG_INDIRECTWR_START,
|
|
plat->regbase + CQSPI_REG_INDIRECTWR);
|
|
|
|
while (remaining > 0) {
|
|
write_bytes = remaining > page_size ? page_size : remaining;
|
|
writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
|
|
if (write_bytes % 4)
|
|
writesb(plat->ahbbase,
|
|
bb_txbuf + rounddown(write_bytes, 4),
|
|
write_bytes % 4);
|
|
|
|
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
|
|
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
|
|
CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
|
|
if (ret) {
|
|
printf("Indirect write timed out (%i)\n", ret);
|
|
goto failwr;
|
|
}
|
|
|
|
bb_txbuf += write_bytes;
|
|
remaining -= write_bytes;
|
|
}
|
|
|
|
/* Check indirect done status */
|
|
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
|
|
CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
|
|
if (ret) {
|
|
printf("Indirect write completion error (%i)\n", ret);
|
|
goto failwr;
|
|
}
|
|
bounce_buffer_stop(&bb);
|
|
|
|
/* Clear indirect completion status */
|
|
writel(CQSPI_REG_INDIRECTWR_DONE,
|
|
plat->regbase + CQSPI_REG_INDIRECTWR);
|
|
return 0;
|
|
|
|
failwr:
|
|
/* Cancel the indirect write */
|
|
writel(CQSPI_REG_INDIRECTWR_CANCEL,
|
|
plat->regbase + CQSPI_REG_INDIRECTWR);
|
|
bounce_buffer_stop(&bb);
|
|
return ret;
|
|
}
|
|
|
|
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
|
|
{
|
|
unsigned int reg;
|
|
|
|
/* enter XiP mode immediately and enable direct mode */
|
|
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
|
reg |= CQSPI_REG_CONFIG_ENABLE;
|
|
reg |= CQSPI_REG_CONFIG_DIRECT;
|
|
reg |= CQSPI_REG_CONFIG_XIP_IMM;
|
|
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
|
|
|
/* keep the XiP mode */
|
|
writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
|
|
|
|
/* Enable mode bit at devrd */
|
|
reg = readl(reg_base + CQSPI_REG_RD_INSTR);
|
|
reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
|
|
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
|
|
}
|
|
|