upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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382 lines
9.9 KiB
382 lines
9.9 KiB
/*
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* Allwinner SUNXI "glue layer"
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*
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* Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
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* Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
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* javen <javen@allwinnertech.com>
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*
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* Based on the DA8xx "glue layer" code.
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* Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/usb_phy.h>
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#include <asm-generic/gpio.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <linux/usb/musb.h>
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#include "linux-compat.h"
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#include "musb_core.h"
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#include "musb_uboot.h"
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/******************************************************************************
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******************************************************************************
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* From the Allwinner driver
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******************************************************************************
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******************************************************************************/
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/******************************************************************************
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* From include/sunxi_usb_bsp.h
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******************************************************************************/
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/* reg offsets */
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#define USBC_REG_o_ISCR 0x0400
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#define USBC_REG_o_PHYCTL 0x0404
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#define USBC_REG_o_PHYBIST 0x0408
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#define USBC_REG_o_PHYTUNE 0x040c
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#define USBC_REG_o_VEND0 0x0043
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/* Interface Status and Control */
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#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
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#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
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#define USBC_BP_ISCR_EXT_ID_STATUS 28
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#define USBC_BP_ISCR_EXT_DM_STATUS 27
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#define USBC_BP_ISCR_EXT_DP_STATUS 26
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#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
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#define USBC_BP_ISCR_MERGED_ID_STATUS 24
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#define USBC_BP_ISCR_ID_PULLUP_EN 17
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#define USBC_BP_ISCR_DPDM_PULLUP_EN 16
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#define USBC_BP_ISCR_FORCE_ID 14
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#define USBC_BP_ISCR_FORCE_VBUS_VALID 12
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#define USBC_BP_ISCR_VBUS_VALID_SRC 10
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#define USBC_BP_ISCR_HOSC_EN 7
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#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
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#define USBC_BP_ISCR_ID_CHANGE_DETECT 5
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#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
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#define USBC_BP_ISCR_IRQ_ENABLE 3
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#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
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#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
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#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
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/******************************************************************************
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* From usbc/usbc.c
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******************************************************************************/
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static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
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{
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u32 temp = reg_val;
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temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
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temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
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temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
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return temp;
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}
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static void USBC_EnableIdPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_EnableDpDmPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceIdToLow(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceIdToHigh(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceVbusValidToLow(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceVbusValidToHigh(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ConfigFIFO_Base(void)
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{
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u32 reg_value;
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/* config usb fifo, 8kb mode */
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reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
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reg_value &= ~(0x03 << 0);
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reg_value |= (1 << 0);
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writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
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}
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/******************************************************************************
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* Needed for the DFU polling magic
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******************************************************************************/
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static u8 last_int_usb;
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bool dfu_usb_get_reset(void)
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{
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return !!(last_int_usb & MUSB_INTR_RESET);
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}
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/******************************************************************************
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* MUSB Glue code
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******************************************************************************/
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static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
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{
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struct musb *musb = __hci;
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irqreturn_t retval = IRQ_NONE;
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/* read and flush interrupts */
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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last_int_usb = musb->int_usb;
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if (musb->int_usb)
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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if (musb->int_tx)
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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if (musb->int_rx)
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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if (musb->int_usb || musb->int_tx || musb->int_rx)
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retval |= musb_interrupt(musb);
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return retval;
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}
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/* musb_core does not call enable / disable in a balanced manner <sigh> */
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static bool enabled = false;
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static int sunxi_musb_enable(struct musb *musb)
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{
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int ret;
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pr_debug("%s():\n", __func__);
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musb_ep_select(musb->mregs, 0);
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musb_writeb(musb->mregs, MUSB_FADDR, 0);
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if (enabled)
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return 0;
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/* select PIO mode */
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musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
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if (is_host_enabled(musb)) {
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ret = sunxi_usb_phy_vbus_detect(0);
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if (ret == 1) {
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printf("A charger is plugged into the OTG: ");
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return -ENODEV;
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}
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ret = sunxi_usb_phy_id_detect(0);
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if (ret == 1) {
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printf("No host cable detected: ");
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return -ENODEV;
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}
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sunxi_usb_phy_power_on(0); /* port power on */
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}
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USBC_ForceVbusValidToHigh(musb->mregs);
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enabled = true;
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return 0;
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}
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static void sunxi_musb_disable(struct musb *musb)
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{
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pr_debug("%s():\n", __func__);
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if (!enabled)
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return;
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if (is_host_enabled(musb))
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sunxi_usb_phy_power_off(0); /* port power off */
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USBC_ForceVbusValidToLow(musb->mregs);
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mdelay(200); /* Wait for the current session to timeout */
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enabled = false;
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}
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static int sunxi_musb_init(struct musb *musb)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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pr_debug("%s():\n", __func__);
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musb->isr = sunxi_musb_interrupt;
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
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#endif
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sunxi_usb_phy_init(0);
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USBC_ConfigFIFO_Base();
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USBC_EnableDpDmPullUp(musb->mregs);
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USBC_EnableIdPullUp(musb->mregs);
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if (is_host_enabled(musb)) {
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/* Host mode */
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USBC_ForceIdToLow(musb->mregs);
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} else {
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/* Peripheral mode */
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USBC_ForceIdToHigh(musb->mregs);
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}
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USBC_ForceVbusValidToHigh(musb->mregs);
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return 0;
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}
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static const struct musb_platform_ops sunxi_musb_ops = {
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.init = sunxi_musb_init,
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.enable = sunxi_musb_enable,
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.disable = sunxi_musb_disable,
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};
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static struct musb_hdrc_config musb_config = {
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.multipoint = 1,
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.dyn_fifo = 1,
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.num_eps = 6,
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.ram_bits = 11,
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};
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static struct musb_hdrc_platform_data musb_plat = {
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#if defined(CONFIG_USB_MUSB_HOST)
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.mode = MUSB_HOST,
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#else
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.mode = MUSB_PERIPHERAL,
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#endif
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.config = &musb_config,
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.power = 250,
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.platform_ops = &sunxi_musb_ops,
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};
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static int musb_usb_probe(struct udevice *dev)
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{
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struct musb_host_data *host = dev_get_priv(dev);
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struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
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void *base = dev_read_addr_ptr(dev);
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int ret;
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if (!base)
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return -EINVAL;
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priv->desc_before_addr = true;
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#ifdef CONFIG_USB_MUSB_HOST
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host->host = musb_init_controller(&musb_plat, NULL, base);
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if (!host->host)
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return -EIO;
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ret = musb_lowlevel_init(host);
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if (!ret)
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printf("Allwinner mUSB OTG (Host)\n");
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#else
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ret = musb_register(&musb_plat, NULL, base);
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if (!ret)
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printf("Allwinner mUSB OTG (Peripheral)\n");
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#endif
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return ret;
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}
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static int musb_usb_remove(struct udevice *dev)
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{
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struct musb_host_data *host = dev_get_priv(dev);
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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musb_stop(host->host);
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sunxi_usb_phy_exit(0);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
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#endif
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
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free(host->host);
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host->host = NULL;
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return 0;
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}
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static const struct udevice_id sunxi_musb_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-musb" },
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{ .compatible = "allwinner,sun6i-a31-musb" },
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{ .compatible = "allwinner,sun8i-a33-musb" },
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{ .compatible = "allwinner,sun8i-h3-musb" },
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{ }
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};
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U_BOOT_DRIVER(usb_musb) = {
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.name = "sunxi-musb",
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#ifdef CONFIG_USB_MUSB_HOST
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.id = UCLASS_USB,
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#else
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.id = UCLASS_USB_DEV_GENERIC,
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#endif
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.of_match = sunxi_musb_ids,
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.probe = musb_usb_probe,
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.remove = musb_usb_remove,
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#ifdef CONFIG_USB_MUSB_HOST
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.ops = &musb_usb_ops,
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#endif
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct musb_host_data),
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};
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