upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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931 lines
27 KiB
931 lines
27 KiB
/**
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* @file IxNpeDlNpeMgr.c
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*
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* @author Intel Corporation
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* @date 09 January 2002
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*
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* @brief This file contains the implementation of the private API for the
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* IXP425 NPE Downloader NpeMgr module
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/*
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* Put the user defined include files required.
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*/
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#include "IxOsal.h"
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#include "IxNpeDl.h"
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#include "IxNpeDlNpeMgr_p.h"
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#include "IxNpeDlNpeMgrUtils_p.h"
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#include "IxNpeDlNpeMgrEcRegisters_p.h"
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#include "IxNpeDlMacros_p.h"
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#include "IxFeatureCtrl.h"
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/*
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* #defines and macros used in this file.
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*/
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#define IX_NPEDL_BYTES_PER_WORD 4
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/* used to read download map from version in microcode image */
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#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000
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#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001
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#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002
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#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F
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/*
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* masks used to extract address info from State information context
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* register addresses as read from microcode image
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*/
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#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F
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#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0
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/* LSB offset of Context Number field in State-Info Context Address */
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#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4
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/* size (in words) of single State Information entry (ctxt reg address|data) */
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#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2
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#define IX_NPEDL_RESET_NPE_PARITY 0x0800
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#define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF
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#define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF
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/*
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* Typedefs whose scope is limited to this file.
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*/
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typedef struct
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{
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UINT32 type;
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UINT32 offset;
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} IxNpeDlNpeMgrDownloadMapBlockEntry;
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typedef union
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{
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IxNpeDlNpeMgrDownloadMapBlockEntry block;
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UINT32 eodmMarker;
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} IxNpeDlNpeMgrDownloadMapEntry;
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typedef struct
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{
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/* 1st entry in the download map (there may be more than one) */
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IxNpeDlNpeMgrDownloadMapEntry entry[1];
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} IxNpeDlNpeMgrDownloadMap;
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/* used to access an instruction or data block in a microcode image */
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typedef struct
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{
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UINT32 npeMemAddress;
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UINT32 size;
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UINT32 data[1];
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} IxNpeDlNpeMgrCodeBlock;
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/* used to access each Context Reg entry state-information block */
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typedef struct
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{
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UINT32 addressInfo;
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UINT32 value;
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} IxNpeDlNpeMgrStateInfoCtxtRegEntry;
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/* used to access a state-information block in a microcode image */
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typedef struct
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{
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UINT32 size;
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IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
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} IxNpeDlNpeMgrStateInfoBlock;
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/* used to store some useful NPE information for easy access */
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typedef struct
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{
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UINT32 baseAddress;
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UINT32 insMemSize;
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UINT32 dataMemSize;
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} IxNpeDlNpeInfo;
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/* used to distinguish instruction and data memory operations */
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typedef enum
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{
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IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
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IX_NPEDL_MEM_TYPE_DATA
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} IxNpeDlNpeMemType;
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/* used to hold a reset value for a particular ECS register */
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typedef struct
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{
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UINT32 regAddr;
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UINT32 regResetVal;
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} IxNpeDlEcsRegResetValue;
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/* prototype of function to write either Instruction or Data memory */
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typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
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UINT32 npeMemAddress,
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UINT32 npeMemData,
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BOOL verify);
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/* module statistics counters */
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typedef struct
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{
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UINT32 instructionBlocksLoaded;
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UINT32 dataBlocksLoaded;
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UINT32 stateInfoBlocksLoaded;
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UINT32 criticalNpeErrors;
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UINT32 criticalMicrocodeErrors;
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UINT32 npeStarts;
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UINT32 npeStops;
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UINT32 npeResets;
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} IxNpeDlNpeMgrStats;
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/*
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* Variable declarations global to this file only. Externs are followed by
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* static variables.
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*/
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static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
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{
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{
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0,
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IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
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IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
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},
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{
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0,
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IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
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IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
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},
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{
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0,
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IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
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IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
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}
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};
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/* contains Reset values for Context Store Registers */
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static UINT32 ixNpeDlCtxtRegResetValues[] =
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{
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IX_NPEDL_CTXT_REG_RESET_STEVT,
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IX_NPEDL_CTXT_REG_RESET_STARTPC,
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IX_NPEDL_CTXT_REG_RESET_REGMAP,
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IX_NPEDL_CTXT_REG_RESET_CINDEX,
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};
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/* contains Reset values for Context Store Registers */
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static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
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{
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{IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
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{IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
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{IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
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{IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
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{IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
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{IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
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{IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
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{IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
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{IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
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{IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
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{IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
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{IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
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{IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET}
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};
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static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
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/* Set when NPE register memory has been mapped */
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static BOOL ixNpeDlMemInitialised = FALSE;
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/*
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* static function prototypes.
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*/
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PRIVATE IX_STATUS
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ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
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IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
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BOOL verify, IxNpeDlNpeMemType npeMemType);
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PRIVATE IX_STATUS
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ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
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IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
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BOOL verify);
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PRIVATE BOOL
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ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
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UINT32 expectedBitsSet);
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PRIVATE UINT32
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ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
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/*
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* Function definition: ixNpeDlNpeMgrBaseAddressGet
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*/
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PRIVATE UINT32
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ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
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{
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IX_OSAL_ASSERT (ixNpeDlMemInitialised);
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return ixNpeDlNpeInfo[npeId].baseAddress;
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}
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/*
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* Function definition: ixNpeDlNpeMgrInit
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*/
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void
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ixNpeDlNpeMgrInit (void)
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{
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/* Only map the memory once */
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if (!ixNpeDlMemInitialised)
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{
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UINT32 virtAddr;
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/* map the register memory for NPE-A */
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virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
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IX_OSAL_IXP400_NPEA_MAP_SIZE);
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IX_OSAL_ASSERT(virtAddr);
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ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
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/* map the register memory for NPE-B */
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virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
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IX_OSAL_IXP400_NPEB_MAP_SIZE);
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IX_OSAL_ASSERT(virtAddr);
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ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
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/* map the register memory for NPE-C */
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virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
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IX_OSAL_IXP400_NPEC_MAP_SIZE);
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IX_OSAL_ASSERT(virtAddr);
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ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
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ixNpeDlMemInitialised = TRUE;
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}
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}
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/*
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* Function definition: ixNpeDlNpeMgrUninit
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*/
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IX_STATUS
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ixNpeDlNpeMgrUninit (void)
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{
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if (!ixNpeDlMemInitialised)
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{
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return IX_FAIL;
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}
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IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
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IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
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IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
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ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
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ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
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ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
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ixNpeDlMemInitialised = FALSE;
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return IX_SUCCESS;
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}
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/*
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* Function definition: ixNpeDlNpeMgrImageLoad
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*/
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IX_STATUS
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ixNpeDlNpeMgrImageLoad (
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IxNpeDlNpeId npeId,
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UINT32 *imageCodePtr,
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BOOL verify)
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{
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UINT32 npeBaseAddress;
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IxNpeDlNpeMgrDownloadMap *downloadMap;
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UINT32 *blockPtr;
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UINT32 mapIndex = 0;
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IX_STATUS status = IX_SUCCESS;
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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"Entering ixNpeDlNpeMgrImageLoad\n");
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/* get base memory address of NPE from npeId */
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npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
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/* check execution status of NPE to verify NPE Stop was successful */
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if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
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IX_NPEDL_EXCTL_STATUS_STOP))
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{
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IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
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"NPE was not stopped before download\n");
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status = IX_FAIL;
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}
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else
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{
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/*
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* Read Download Map, checking each block type and calling
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* appropriate function to perform download
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*/
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downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
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while ((downloadMap->entry[mapIndex].eodmMarker !=
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IX_NPEDL_END_OF_DOWNLOAD_MAP)
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&& (status == IX_SUCCESS))
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{
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/* calculate pointer to block to be downloaded */
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blockPtr = imageCodePtr +
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downloadMap->entry[mapIndex].block.offset;
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switch (downloadMap->entry[mapIndex].block.type)
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{
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case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
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status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
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(IxNpeDlNpeMgrCodeBlock *)blockPtr,
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verify,
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IX_NPEDL_MEM_TYPE_INSTRUCTION);
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break;
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case IX_NPEDL_BLOCK_TYPE_DATA:
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status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
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(IxNpeDlNpeMgrCodeBlock *)blockPtr,
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verify, IX_NPEDL_MEM_TYPE_DATA);
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break;
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case IX_NPEDL_BLOCK_TYPE_STATE:
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status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
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(IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
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verify);
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break;
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default:
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IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
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"unknown block type in download map\n");
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status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
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ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
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break;
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}
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mapIndex++;
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}/* loop: for each entry in download map, while status == SUCCESS */
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}/* condition: NPE stopped before attempting download */
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IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
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"Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
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status);
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return status;
|
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}
|
|
|
|
|
|
/*
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* Function definition: ixNpeDlNpeMgrMemLoad
|
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*/
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PRIVATE IX_STATUS
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ixNpeDlNpeMgrMemLoad (
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IxNpeDlNpeId npeId,
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UINT32 npeBaseAddress,
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IxNpeDlNpeMgrCodeBlock *blockPtr,
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BOOL verify,
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IxNpeDlNpeMemType npeMemType)
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{
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UINT32 npeMemAddress;
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UINT32 blockSize;
|
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UINT32 memSize = 0;
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IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
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UINT32 localIndex = 0;
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IX_STATUS status = IX_SUCCESS;
|
|
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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"Entering ixNpeDlNpeMgrMemLoad\n");
|
|
|
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/*
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* select NPE EXCTL reg read/write commands depending on memory
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* type (instruction/data) to be accessed
|
|
*/
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if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
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{
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memSize = ixNpeDlNpeInfo[npeId].insMemSize;
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memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
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}
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else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
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{
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memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
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memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
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}
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|
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/*
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* NPE memory is loaded contiguously from each block, so only address
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* of 1st word in block is needed
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|
*/
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npeMemAddress = blockPtr->npeMemAddress;
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/* number of words of instruction/data microcode in block to download */
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|
blockSize = blockPtr->size;
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if ((npeMemAddress + blockSize) > memSize)
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{
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IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
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"Block size too big for NPE memory\n");
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status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
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ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
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}
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else
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{
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for (localIndex = 0; localIndex < blockSize; localIndex++)
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|
{
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status = memWriteFunc (npeBaseAddress, npeMemAddress,
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blockPtr->data[localIndex], verify);
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|
|
if (status != IX_SUCCESS)
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{
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IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
|
|
"write to NPE memory failed\n");
|
|
status = IX_NPEDL_CRITICAL_NPE_ERR;
|
|
ixNpeDlNpeMgrStats.criticalNpeErrors++;
|
|
break; /* abort download */
|
|
}
|
|
/* increment target (word)address in NPE memory */
|
|
npeMemAddress++;
|
|
}
|
|
}/* condition: block size will fit in NPE memory */
|
|
|
|
if (status == IX_SUCCESS)
|
|
{
|
|
if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
|
|
{
|
|
ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
|
|
}
|
|
else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
|
|
{
|
|
ixNpeDlNpeMgrStats.dataBlocksLoaded++;
|
|
}
|
|
}
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrStateInfoLoad
|
|
*/
|
|
PRIVATE IX_STATUS
|
|
ixNpeDlNpeMgrStateInfoLoad (
|
|
UINT32 npeBaseAddress,
|
|
IxNpeDlNpeMgrStateInfoBlock *blockPtr,
|
|
BOOL verify)
|
|
{
|
|
UINT32 blockSize;
|
|
UINT32 ctxtRegAddrInfo;
|
|
UINT32 ctxtRegVal;
|
|
IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
|
|
UINT32 ctxtNum; /* identifies Context number (0-16) */
|
|
UINT32 i;
|
|
IX_STATUS status = IX_SUCCESS;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrStateInfoLoad\n");
|
|
|
|
/* block size contains number of words of state-info in block */
|
|
blockSize = blockPtr->size;
|
|
|
|
ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
|
|
|
|
/* for each state-info context register entry in block */
|
|
for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
|
|
{
|
|
/* each state-info entry is 2 words (address, value) in length */
|
|
ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
|
|
ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value;
|
|
|
|
ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
|
|
ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
|
|
IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
|
|
|
|
/* error-check Context Register No. and Context Number values */
|
|
/* NOTE that there is no STEVT register for Context 0 */
|
|
if ((ctxtReg < 0) ||
|
|
(ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
|
|
(ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
|
|
((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
|
|
{
|
|
IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
|
|
"invalid Context Register Address\n");
|
|
status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
|
|
ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
|
|
break; /* abort download */
|
|
}
|
|
|
|
status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
|
|
ctxtRegVal, verify);
|
|
if (status != IX_SUCCESS)
|
|
{
|
|
IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
|
|
"write of state-info to NPE failed\n");
|
|
status = IX_NPEDL_CRITICAL_NPE_ERR;
|
|
ixNpeDlNpeMgrStats.criticalNpeErrors++;
|
|
break; /* abort download */
|
|
}
|
|
}/* loop: for each context reg entry in State Info block */
|
|
|
|
ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
|
|
|
|
if (status == IX_SUCCESS)
|
|
{
|
|
ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
|
|
}
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
|
|
status);
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrNpeReset
|
|
*/
|
|
IX_STATUS
|
|
ixNpeDlNpeMgrNpeReset (
|
|
IxNpeDlNpeId npeId)
|
|
{
|
|
UINT32 npeBaseAddress;
|
|
IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
|
|
UINT32 ctxtNum; /* identifies Context number (0-16) */
|
|
UINT32 regAddr;
|
|
UINT32 regVal;
|
|
UINT32 localIndex;
|
|
UINT32 indexMax;
|
|
IX_STATUS status = IX_SUCCESS;
|
|
IxFeatureCtrlReg unitFuseReg;
|
|
UINT32 ixNpeConfigCtrlRegVal;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrNpeReset\n");
|
|
|
|
/* get base memory address of NPE from npeId */
|
|
npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
|
|
|
|
/* pre-store the NPE Config Control Register Value */
|
|
IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
|
|
|
|
ixNpeConfigCtrlRegVal |= 0x3F000000;
|
|
|
|
/* disable the parity interrupt */
|
|
IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
|
|
|
|
ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
|
|
|
|
/*
|
|
* clear the FIFOs
|
|
*/
|
|
while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
|
|
IX_NPEDL_REG_OFFSET_WFIFO,
|
|
IX_NPEDL_MASK_WFIFO_VALID))
|
|
{
|
|
/* read from the Watch-point FIFO until empty */
|
|
IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
|
|
®Val);
|
|
}
|
|
|
|
while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
|
|
IX_NPEDL_REG_OFFSET_STAT,
|
|
IX_NPEDL_MASK_STAT_OFNE))
|
|
{
|
|
/* read from the outFIFO until empty */
|
|
IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
|
|
®Val);
|
|
}
|
|
|
|
while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
|
|
IX_NPEDL_REG_OFFSET_STAT,
|
|
IX_NPEDL_MASK_STAT_IFNE))
|
|
{
|
|
/*
|
|
* step execution of the NPE intruction to read inFIFO using
|
|
* the Debug Executing Context stack
|
|
*/
|
|
status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
|
|
IX_NPEDL_INSTR_RD_FIFO, 0, 0);
|
|
|
|
if (IX_SUCCESS != status)
|
|
{
|
|
return status;
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
* Reset the mailbox reg
|
|
*/
|
|
/* ...from XScale side */
|
|
IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
|
|
IX_NPEDL_REG_RESET_MBST);
|
|
/* ...from NPE side */
|
|
status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
|
|
IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
|
|
|
|
if (IX_SUCCESS != status)
|
|
{
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Reset the physical registers in the NPE register file:
|
|
* Note: no need to save/restore REGMAP for Context 0 here
|
|
* since all Context Store regs are reset in subsequent code
|
|
*/
|
|
for (regAddr = 0;
|
|
(regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
|
|
regAddr++)
|
|
{
|
|
/* for each physical register in the NPE reg file, write 0 : */
|
|
status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
|
|
0, TRUE);
|
|
if (status != IX_SUCCESS)
|
|
{
|
|
return status; /* abort reset */
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Reset the context store:
|
|
*/
|
|
for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
|
|
ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
|
|
{
|
|
/* set each context's Context Store registers to reset values: */
|
|
for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
|
|
{
|
|
/* NOTE that there is no STEVT register for Context 0 */
|
|
if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
|
|
{
|
|
regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
|
|
status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
|
|
ctxtReg, regVal, TRUE);
|
|
if (status != IX_SUCCESS)
|
|
{
|
|
return status; /* abort reset */
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
|
|
|
|
/* write Reset values to Execution Context Stack registers */
|
|
indexMax = sizeof (ixNpeDlEcsRegResetValues) /
|
|
sizeof (IxNpeDlEcsRegResetValue);
|
|
for (localIndex = 0; localIndex < indexMax; localIndex++)
|
|
{
|
|
regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
|
|
regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
|
|
ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
|
|
}
|
|
|
|
/* clear the profile counter */
|
|
ixNpeDlNpeMgrCommandIssue (npeBaseAddress,
|
|
IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
|
|
|
|
/* clear registers EXCT, AP0, AP1, AP2 and AP3 */
|
|
for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
|
|
regAddr <= IX_NPEDL_REG_OFFSET_AP3;
|
|
regAddr += IX_NPEDL_BYTES_PER_WORD)
|
|
{
|
|
IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
|
|
}
|
|
|
|
/* Reset the Watch-count register */
|
|
IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
|
|
|
|
/*
|
|
* WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
|
|
*/
|
|
|
|
/*
|
|
* Call the feature control API to fused out and reset the NPE and its
|
|
* coprocessor - to reset internal states and remove parity error
|
|
*/
|
|
unitFuseReg = ixFeatureCtrlRead ();
|
|
unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
|
|
ixFeatureCtrlWrite (unitFuseReg);
|
|
|
|
/* call the feature control API to un-fused and un-reset the NPE & COP */
|
|
unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
|
|
ixFeatureCtrlWrite (unitFuseReg);
|
|
|
|
/*
|
|
* Call NpeMgr function to stop the NPE again after the Feature Control
|
|
* has unfused and Un-Reset the NPE and its associated Coprocessors
|
|
*/
|
|
status = ixNpeDlNpeMgrNpeStop (npeId);
|
|
|
|
/* restore NPE configuration bus Control Register - Parity Settings */
|
|
IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL,
|
|
(ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
|
|
|
|
ixNpeDlNpeMgrStats.npeResets++;
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrNpeStart
|
|
*/
|
|
IX_STATUS
|
|
ixNpeDlNpeMgrNpeStart (
|
|
IxNpeDlNpeId npeId)
|
|
{
|
|
UINT32 npeBaseAddress;
|
|
UINT32 ecsRegVal;
|
|
BOOL npeRunning;
|
|
IX_STATUS status = IX_SUCCESS;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrNpeStart\n");
|
|
|
|
/* get base memory address of NPE from npeId */
|
|
npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
|
|
|
|
/*
|
|
* ensure only Background Context Stack Level is Active by turning off
|
|
* the Active bit in each of the other Executing Context Stack levels
|
|
*/
|
|
ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
|
|
IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
|
|
ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
|
|
ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
|
|
ecsRegVal);
|
|
|
|
ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
|
|
IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
|
|
ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
|
|
ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
|
|
ecsRegVal);
|
|
|
|
ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
|
|
IX_NPEDL_ECS_DBG_CTXT_REG_0);
|
|
ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
|
|
ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
|
|
ecsRegVal);
|
|
|
|
/* clear the pipeline */
|
|
ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
|
|
|
|
/* start NPE execution by issuing command through EXCTL register on NPE */
|
|
ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
|
|
|
|
/*
|
|
* check execution status of NPE to verify NPE Start operation was
|
|
* successful
|
|
*/
|
|
npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
|
|
IX_NPEDL_REG_OFFSET_EXCTL,
|
|
IX_NPEDL_EXCTL_STATUS_RUN);
|
|
if (npeRunning)
|
|
{
|
|
ixNpeDlNpeMgrStats.npeStarts++;
|
|
}
|
|
else
|
|
{
|
|
IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
|
|
"failed to start NPE execution\n");
|
|
status = IX_FAIL;
|
|
}
|
|
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrNpeStop
|
|
*/
|
|
IX_STATUS
|
|
ixNpeDlNpeMgrNpeStop (
|
|
IxNpeDlNpeId npeId)
|
|
{
|
|
UINT32 npeBaseAddress;
|
|
IX_STATUS status = IX_SUCCESS;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrNpeStop\n");
|
|
|
|
/* get base memory address of NPE from npeId */
|
|
npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
|
|
|
|
/* stop NPE execution by issuing command through EXCTL register on NPE */
|
|
ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
|
|
|
|
/* verify that NPE Stop was successful */
|
|
if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
|
|
IX_NPEDL_EXCTL_STATUS_STOP))
|
|
{
|
|
IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
|
|
"failed to stop NPE execution\n");
|
|
status = IX_FAIL;
|
|
}
|
|
|
|
ixNpeDlNpeMgrStats.npeStops++;
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrBitsSetCheck
|
|
*/
|
|
PRIVATE BOOL
|
|
ixNpeDlNpeMgrBitsSetCheck (
|
|
UINT32 npeBaseAddress,
|
|
UINT32 regOffset,
|
|
UINT32 expectedBitsSet)
|
|
{
|
|
UINT32 regVal;
|
|
IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val);
|
|
|
|
return expectedBitsSet == (expectedBitsSet & regVal);
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrStatsShow
|
|
*/
|
|
void
|
|
ixNpeDlNpeMgrStatsShow (void)
|
|
{
|
|
ixOsalLog (IX_OSAL_LOG_LVL_USER,
|
|
IX_OSAL_LOG_DEV_STDOUT,
|
|
"\nixNpeDlNpeMgrStatsShow:\n"
|
|
"\tInstruction Blocks loaded: %u\n"
|
|
"\tData Blocks loaded: %u\n"
|
|
"\tState Information Blocks loaded: %u\n"
|
|
"\tCritical NPE errors: %u\n"
|
|
"\tCritical Microcode errors: %u\n",
|
|
ixNpeDlNpeMgrStats.instructionBlocksLoaded,
|
|
ixNpeDlNpeMgrStats.dataBlocksLoaded,
|
|
ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
|
|
ixNpeDlNpeMgrStats.criticalNpeErrors,
|
|
ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
|
|
0);
|
|
|
|
ixOsalLog (IX_OSAL_LOG_LVL_USER,
|
|
IX_OSAL_LOG_DEV_STDOUT,
|
|
"\tSuccessful NPE Starts: %u\n"
|
|
"\tSuccessful NPE Stops: %u\n"
|
|
"\tSuccessful NPE Resets: %u\n\n",
|
|
ixNpeDlNpeMgrStats.npeStarts,
|
|
ixNpeDlNpeMgrStats.npeStops,
|
|
ixNpeDlNpeMgrStats.npeResets,
|
|
0,0,0);
|
|
|
|
ixNpeDlNpeMgrUtilsStatsShow ();
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrStatsReset
|
|
*/
|
|
void
|
|
ixNpeDlNpeMgrStatsReset (void)
|
|
{
|
|
ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
|
|
ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
|
|
ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
|
|
ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
|
|
ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
|
|
ixNpeDlNpeMgrStats.npeStarts = 0;
|
|
ixNpeDlNpeMgrStats.npeStops = 0;
|
|
ixNpeDlNpeMgrStats.npeResets = 0;
|
|
|
|
ixNpeDlNpeMgrUtilsStatsReset ();
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}
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|