upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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16 KiB
555 lines
16 KiB
/**
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* @file IxNpeMhConfig_p.h
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*
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* @author Intel Corporation
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* @date 18 Jan 2002
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*
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* @brief This file contains the private API for the Configuration module.
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/**
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* @defgroup IxNpeMhConfig_p IxNpeMhConfig_p
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*
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* @brief The private API for the Configuration module.
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*
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* @{
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*/
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#ifndef IXNPEMHCONFIG_P_H
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#define IXNPEMHCONFIG_P_H
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#include "IxOsal.h"
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#include "IxNpeMh.h"
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#include "IxNpeMhMacros_p.h"
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/*
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* inline definition
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*/
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/* enable function inlining for performances */
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#ifdef IXNPEMHSOLICITEDCBMGR_C
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/* Non-inline functions will be defined in this translation unit.
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Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline
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functions will not be compiled.
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*/
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# ifndef __wince
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# ifndef IXNPEMHCONFIG_INLINE
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# define IXNPEMHCONFIG_INLINE
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# endif
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# else
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# ifndef IXNPEMHCONFIG_INLINE
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# define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
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# endif
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# endif /* __wince*/
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#else
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# ifndef IXNPEMHCONFIG_INLINE
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# define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
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# endif /* IXNPEMHCONFIG_INLINE */
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#endif /* IXNPEMHSOLICITEDCBMGR_C */
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/*
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* Typedefs and #defines, etc.
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*/
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typedef void (*IxNpeMhConfigIsr) (int); /**< ISR function pointer */
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/**
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* @struct IxNpeMhConfigNpeInfo
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*
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* @brief This structure is used to maintain the configuration information
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* associated with an NPE.
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*/
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typedef struct
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{
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IxOsalMutex mutex; /**< mutex */
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UINT32 interruptId; /**< interrupt ID */
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UINT32 virtualRegisterBase; /**< register virtual base address */
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UINT32 statusRegister; /**< status register virtual address */
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UINT32 controlRegister; /**< control register virtual address */
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UINT32 inFifoRegister; /**< inFIFO register virutal address */
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UINT32 outFifoRegister; /**< outFIFO register virtual address */
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IxNpeMhConfigIsr isr; /**< isr routine for handling interrupt */
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BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */
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} IxNpeMhConfigNpeInfo;
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/*
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* #defines for function return types, etc.
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*/
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/**< NPE register base address */
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#define IX_NPEMH_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
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#define IX_NPEMH_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
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#define IX_NPEMH_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
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#define IX_NPEMH_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
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#define IX_NPEMH_NPESTAT_OFFSET (0x002C) /**< NPE status register offset */
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#define IX_NPEMH_NPECTL_OFFSET (0x0030) /**< NPE control register offset */
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#define IX_NPEMH_NPEFIFO_OFFSET (0x0038) /**< NPE FIFO register offset */
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/** NPE-A register base address */
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#define IX_NPEMH_NPEA_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEA_OFFSET)
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/** NPE-B register base address */
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#define IX_NPEMH_NPEB_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEB_OFFSET)
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/** NPE-C register base address */
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#define IX_NPEMH_NPEC_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEC_OFFSET)
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/* NPE-A configuration */
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/** NPE-A interrupt */
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#define IX_NPEMH_NPEA_INT (IX_OSAL_IXP400_NPEA_IRQ_LVL)
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/** NPE-A FIFO register */
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#define IX_NPEMH_NPEA_FIFO (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPEFIFO_OFFSET)
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/** NPE-A control register */
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#define IX_NPEMH_NPEA_CTL (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPECTL_OFFSET)
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/** NPE-A status register */
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#define IX_NPEMH_NPEA_STAT (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPESTAT_OFFSET)
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/* NPE-B configuration */
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/** NPE-B interrupt */
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#define IX_NPEMH_NPEB_INT (IX_OSAL_IXP400_NPEB_IRQ_LVL)
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/** NPE-B FIFO register */
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#define IX_NPEMH_NPEB_FIFO (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPEFIFO_OFFSET)
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/** NPE-B control register */
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#define IX_NPEMH_NPEB_CTL (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPECTL_OFFSET)
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/** NPE-B status register */
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#define IX_NPEMH_NPEB_STAT (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPESTAT_OFFSET)
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/* NPE-C configuration */
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/** NPE-C interrupt */
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#define IX_NPEMH_NPEC_INT (IX_OSAL_IXP400_NPEC_IRQ_LVL)
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/** NPE-C FIFO register */
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#define IX_NPEMH_NPEC_FIFO (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPEFIFO_OFFSET)
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/** NPE-C control register */
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#define IX_NPEMH_NPEC_CTL (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPECTL_OFFSET)
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/** NPE-C status register */
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#define IX_NPEMH_NPEC_STAT (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPESTAT_OFFSET)
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/* NPE control register bit definitions */
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#define IX_NPEMH_NPE_CTL_OFE (1 << 16) /**< OutFifoEnable */
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#define IX_NPEMH_NPE_CTL_IFE (1 << 17) /**< InFifoEnable */
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#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */
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#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */
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/* NPE status register bit definitions */
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#define IX_NPEMH_NPE_STAT_OFNE (1 << 16) /**< OutFifoNotEmpty */
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#define IX_NPEMH_NPE_STAT_IFNF (1 << 17) /**< InFifoNotFull */
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#define IX_NPEMH_NPE_STAT_OFNF (1 << 18) /**< OutFifoNotFull */
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#define IX_NPEMH_NPE_STAT_IFNE (1 << 19) /**< InFifoNotEmpty */
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#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */
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#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */
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#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */
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#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */
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/**
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* Variable declarations. Externs are followed by static variables.
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*/
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extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
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/*
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* Prototypes for interface functions.
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*/
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/**
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* @fn void ixNpeMhConfigInitialize (
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IxNpeMhNpeInterrupts npeInterrupts)
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*
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* @brief This function initialises the Configuration module.
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*
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* @param IxNpeMhNpeInterrupts npeInterrupts (in) - whether or not to
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* service the NPE "outFIFO not empty" interrupts.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigInitialize (
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IxNpeMhNpeInterrupts npeInterrupts);
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/**
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* @fn void ixNpeMhConfigUninit (void)
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*
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* @brief This function uninitialises the Configuration module.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigUninit (void);
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/**
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* @fn void ixNpeMhConfigIsrRegister (
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IxNpeMhNpeId npeId,
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IxNpeMhConfigIsr isr)
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*
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* @brief This function registers an ISR to handle NPE "outFIFO not
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* empty" interrupts.
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*
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* @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
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* be handled.
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* @param IxNpeMhConfigIsr isr (in) - the ISR function pointer that the
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* interrupt will trigger.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigIsrRegister (
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IxNpeMhNpeId npeId,
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IxNpeMhConfigIsr isr);
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/**
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* @fn BOOL ixNpeMhConfigNpeInterruptEnable (
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IxNpeMhNpeId npeId)
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*
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* @brief This function enables a NPE's "outFIFO not empty" interrupt.
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*
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* @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
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* be enabled.
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*
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* @return Returns the previous state of the interrupt (TRUE => enabled).
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*/
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BOOL ixNpeMhConfigNpeInterruptEnable (
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IxNpeMhNpeId npeId);
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/**
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* @fn BOOL ixNpeMhConfigNpeInterruptDisable (
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IxNpeMhNpeId npeId)
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*
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* @brief This function disables a NPE's "outFIFO not empty" interrupt
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*
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* @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
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* be disabled.
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*
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* @return Returns the previous state of the interrupt (TRUE => enabled).
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*/
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BOOL ixNpeMhConfigNpeInterruptDisable (
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IxNpeMhNpeId npeId);
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/**
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* @fn IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
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IxNpeMhMessage message)
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*
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* @brief This function gets the ID of a message.
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*
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* @param IxNpeMhMessage message (in) - the message to get the ID of.
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*
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* @return the ID of the message
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*/
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IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
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IxNpeMhMessage message);
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/**
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* @fn BOOL ixNpeMhConfigNpeIdIsValid (
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IxNpeMhNpeId npeId)
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*
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* @brief This function checks to see if a NPE ID is valid.
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*
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* @param IxNpeMhNpeId npeId (in) - the NPE ID to validate.
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*
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* @return True if the NPE ID is valid, otherwise False.
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*/
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BOOL ixNpeMhConfigNpeIdIsValid (
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IxNpeMhNpeId npeId);
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/**
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* @fn void ixNpeMhConfigLockGet (
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IxNpeMhNpeId npeId)
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*
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* @brief This function gets a lock for exclusive NPE interaction, and
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* disables the NPE's "outFIFO not empty" interrupt.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to get the
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* lock and disable its interrupt.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigLockGet (
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IxNpeMhNpeId npeId);
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/**
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* @fn void ixNpeMhConfigLockRelease (
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IxNpeMhNpeId npeId)
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*
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* @brief This function releases a lock for exclusive NPE interaction, and
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* enables the NPE's "outFIFO not empty" interrupt.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to release
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* the lock and enable its interrupt.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigLockRelease (
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IxNpeMhNpeId npeId);
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/**
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* @fn BOOL ixNpeMhConfigInFifoIsEmpty (
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IxNpeMhNpeId npeId)
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*
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* @brief This inline function checks if a NPE's inFIFO is empty.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
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* will be checked.
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*
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* @return True if the inFIFO is empty, otherwise False.
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*/
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IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty (
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IxNpeMhNpeId npeId);
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/**
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* @fn BOOL ixNpeMhConfigInFifoIsFull (
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IxNpeMhNpeId npeId)
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*
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* @brief This inline function checks if a NPE's inFIFO is full.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
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* will be checked.
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*
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* @return True if the inFIFO is full, otherwise False.
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*/
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IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull (
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IxNpeMhNpeId npeId);
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/**
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* @fn BOOL ixNpeMhConfigOutFifoIsEmpty (
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IxNpeMhNpeId npeId)
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*
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* @brief This inline function checks if a NPE's outFIFO is empty.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
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* will be checked.
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*
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* @return True if the outFIFO is empty, otherwise False.
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*/
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IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty (
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IxNpeMhNpeId npeId);
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/**
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* @fn BOOL ixNpeMhConfigOutFifoIsFull (
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IxNpeMhNpeId npeId)
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*
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* @brief This inline function checks if a NPE's outFIFO is full.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
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* will be checked.
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*
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* @return True if the outFIFO is full, otherwise False.
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*/
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IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull (
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IxNpeMhNpeId npeId);
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/**
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* @fn IX_STATUS ixNpeMhConfigInFifoWrite (
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IxNpeMhNpeId npeId,
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IxNpeMhMessage message)
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*
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* @brief This function writes a message to a NPE's inFIFO. The caller
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* must first check that the NPE's inFifo is not full. After writing the first
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* word of the message, this function will keep polling NPE's inFIFO is not
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* full to write the second word. If inFIFO is not available after maximum
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* retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT
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* status to indicate NPE hang / halt.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
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* will be written to.
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* @param IxNpeMhMessage message (in) - The message to write.
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*
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* @return The function returns a status indicating success, failure or timeout.
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*/
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IX_STATUS ixNpeMhConfigInFifoWrite (
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IxNpeMhNpeId npeId,
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IxNpeMhMessage message);
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/**
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* @fn IX_STATUS ixNpeMhConfigOutFifoRead (
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IxNpeMhNpeId npeId,
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IxNpeMhMessage *message)
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*
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* @brief This function reads a message from a NPE's outFIFO. The caller
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* must first check that the NPE's outFifo is not empty. After reading the first
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* word of the message, this function will keep polling NPE's outFIFO is not
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* empty to read the second word. If outFIFO is empty after maximum
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* retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT
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* status to indicate NPE hang / halt.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
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* will be read from.
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* @param IxNpeMhMessage message (out) - The message read.
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*
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* @return The function returns a status indicating success, failure or timeout.
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*/
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IX_STATUS ixNpeMhConfigOutFifoRead (
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IxNpeMhNpeId npeId,
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IxNpeMhMessage *message);
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/**
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* @fn void ixNpeMhConfigShow (
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IxNpeMhNpeId npeId)
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*
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* @brief This function will display the current state of the Configuration
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* module.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
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* information for.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigShow (
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IxNpeMhNpeId npeId);
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/**
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* @fn void ixNpeMhConfigShowReset (
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IxNpeMhNpeId npeId)
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*
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* @brief This function will reset the current state of the Configuration
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* module.
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*
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* @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
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* information for.
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*
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* @return No return value.
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*/
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void ixNpeMhConfigShowReset (
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IxNpeMhNpeId npeId);
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/*
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* Inline functions
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*/
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/*
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* This inline function checks if a NPE's inFIFO is empty.
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*/
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IXNPEMHCONFIG_INLINE
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BOOL ixNpeMhConfigInFifoIsEmpty (
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IxNpeMhNpeId npeId)
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{
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UINT32 ifne;
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volatile UINT32 *statusReg =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
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/* get the IFNE (InFifoNotEmpty) bit of the status register */
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IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifne, IX_NPEMH_NPE_STAT_IFNE);
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/* if the IFNE status bit is unset then the inFIFO is empty */
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return (ifne == 0);
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}
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/*
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* This inline function checks if a NPE's inFIFO is full.
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*/
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IXNPEMHCONFIG_INLINE
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BOOL ixNpeMhConfigInFifoIsFull (
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IxNpeMhNpeId npeId)
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{
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UINT32 ifnf;
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volatile UINT32 *statusReg =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
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/* get the IFNF (InFifoNotFull) bit of the status register */
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IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_NPEMH_NPE_STAT_IFNF);
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/* if the IFNF status bit is unset then the inFIFO is full */
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return (ifnf == 0);
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}
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/*
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* This inline function checks if a NPE's outFIFO is empty.
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*/
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IXNPEMHCONFIG_INLINE
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BOOL ixNpeMhConfigOutFifoIsEmpty (
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IxNpeMhNpeId npeId)
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{
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UINT32 ofne;
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volatile UINT32 *statusReg =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
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/* get the OFNE (OutFifoNotEmpty) bit of the status register */
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IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofne, IX_NPEMH_NPE_STAT_OFNE);
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/* if the OFNE status bit is unset then the outFIFO is empty */
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return (ofne == 0);
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}
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/*
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* This inline function checks if a NPE's outFIFO is full.
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*/
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IXNPEMHCONFIG_INLINE
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BOOL ixNpeMhConfigOutFifoIsFull (
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IxNpeMhNpeId npeId)
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{
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UINT32 ofnf;
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volatile UINT32 *statusReg =
|
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
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/* get the OFNF (OutFifoNotFull) bit of the status register */
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IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_NPEMH_NPE_STAT_OFNF);
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/* if the OFNF status bit is unset then the outFIFO is full */
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return (ofnf == 0);
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}
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#endif /* IXNPEMHCONFIG_P_H */
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/**
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* @} defgroup IxNpeMhConfig_p
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*/
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