upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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242 lines
7.6 KiB
242 lines
7.6 KiB
/*
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* (C) Copyright 2009
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* Michael Schwingen, michael@schwingen.org
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*
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* Configuration settings for the
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* dLAN200 AV Wireless G ("dvlhost") board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_IXP425 1
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#define CONFIG_DVLHOST 1
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#define CONFIG_MACH_TYPE 1343
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_IXP_SERIAL
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds"
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/***************************************************************
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* U-boot generic defines start here.
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***************************************************************/
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command line configuration. */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_PCI
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_IXP_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI_ENUM
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#endif
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#define CONFIG_BOOTCOMMAND "run boot_flash"
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_KGDB_BAUDRATE 230400
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/* which serial port to use */
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# define CONFIG_KGDB_SER_INDEX 1
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00000000
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#define CONFIG_SYS_MEMTEST_END 0x01D80000
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/* timer clock - 2* OSC_IN system clock */
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#define CONFIG_IXP425_TIMER_CLK 66666666
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#define CONFIG_SYS_HZ 1000
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
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115200, 230400 }
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#define CONFIG_SERIAL_RTS_ACTIVE 1
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/* Expansion bus settings */
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#define CONFIG_SYS_EXP_CS0 0xbd113442
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/* SDRAM settings */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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/* 32MB SDRAM: 2* 8Mx16, CL3 */
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#define CONFIG_SYS_SDR_CONFIG 0x18
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#define PHYS_SDRAM_1_SIZE 0x02000000
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#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800
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#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
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#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
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/* FLASH organization: one Spansion S29AL032D-04 Flash */
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 140
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#define PHYS_FLASH_1 0x50000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_BOARD_SIZE_LIMIT 262144
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/* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* no byte writes on IXP4xx */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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/* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Ethernet */
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/* include IXP4xx NPE support */
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#define CONFIG_IXP4XX_NPE 1
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/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */
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#define CONFIG_PHY_ADDR 0x18
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/* NPE1 PHY: MII IP175 switch, port 5 is host port */
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#define CONFIG_PHY1_ADDR 0x05
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/* MII PHY management */
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#define CONFIG_MII 1
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/* fixed-speed powerline modem without standard PHY registers on MII */
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#define CONFIG_MII_NPE0_FIXEDLINK 1
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#define CONFIG_MII_NPE0_SPEED 100
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#define CONFIG_MII_NPE0_FULLDUPLEX 1
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/* fixed-speed switch without standard PHY registers on MII */
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#define CONFIG_MII_NPE1_FIXEDLINK 1
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#define CONFIG_MII_NPE1_SPEED 100
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#define CONFIG_MII_NPE1_FULLDUPLEX 1
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/* Number of ethernet rx buffers & descriptors */
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_RESET_PHY_R 1
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/* ethernet switch connected to MII port */
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#define CONFIG_MII_ETHSWITCH 1
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#undef CONFIG_CMD_NFS
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*
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* environment organization:
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* one flash sector, embedded in uboot area (bottom bootblock flash)
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
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#define CONFIG_SYS_USE_PPCENV 1
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"npe_ucode=50040000\0" \
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"ethprime=NPE1\0" \
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"ethrotate=no\0" \
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"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \
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"kerneladdr=50050000\0" \
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"kernelfile=dvlhost/uImage\0" \
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"rootfile=dvlhost/rootfs\0" \
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"rootaddr=50170000\0" \
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"loadaddr=10000\0" \
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"updateboot_ser=mw.b 10000 ff 40000;" \
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" loady ${loadaddr};" \
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" run eraseboot writeboot\0" \
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"updateboot_net=mw.b 10000 ff 40000;" \
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" tftp ${loadaddr} dvlhost/u-boot.bin;" \
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" run eraseboot writeboot\0" \
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"eraseboot=protect off 50000000 50003fff;" \
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" protect off 50006000 5003ffff;" \
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" erase 50000000 50003fff;" \
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" erase 50006000 5003ffff\0" \
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"writeboot=cp.b 10000 50000000 4000;" \
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" cp.b 16000 50006000 3a000\0" \
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"updateucode=loady;" \
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" era ${npe_ucode} +${filesize};" \
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" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
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"updateroot=tftp ${loadaddr} ${rootfile};" \
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" era ${rootaddr} +${filesize};" \
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" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
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"updatekern=tftp ${loadaddr} ${kernelfile};" \
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" era ${kerneladdr} +${filesize};" \
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" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
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"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
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"boot_flash=run flashargs addtty addeth;" \
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" bootm ${kerneladdr}\0" \
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"boot_net=run netargs addtty addeth;" \
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" tftpboot ${loadaddr} ${kernelfile};" \
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" bootm\0"
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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