upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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619 lines
23 KiB
619 lines
23 KiB
/*
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/ibmpc.h>
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SYS_SC520
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#define CONFIG_SYS_SC520_SSI
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_LAST_STAGE_INIT
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/*-----------------------------------------------------------------------
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* Watchdog Configuration
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* NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
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* bottom (processor) board MUST be removed!
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*/
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#undef CONFIG_WATCHDOG
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#define CONFIG_HW_WATCHDOG
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/*-----------------------------------------------------------------------
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* Real Time Clock Configuration
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*/
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#define CONFIG_RTC_MC146818
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
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/*-----------------------------------------------------------------------
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* Serial Configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 1843200
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
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9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 UART0_BASE
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#define CONFIG_SYS_NS16550_COM2 UART1_BASE
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#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
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#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
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#define CONFIG_SYS_NS16550_PORT_MAPPED
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/*-----------------------------------------------------------------------
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* Video Configuration
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*/
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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/*-----------------------------------------------------------------------
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_IMLS
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ITEST
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_SETGETDCR
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#define CONFIG_CMD_SOURCE
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#define CONFIG_CMD_XIMG
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#define CONFIG_CMD_ZBOOT
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#define CONFIG_BOOTDELAY 15
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200
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#define CONFIG_KGDB_SER_INDEX 2
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "boot > "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + \
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16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00100000
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#define CONFIG_SYS_MEMTEST_END 0x01000000
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* SDRAM Configuration
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*/
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#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
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#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
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#define CONFIG_NR_DRAM_BANKS 4
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/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
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#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
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#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
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#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
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#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
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/*-----------------------------------------------------------------------
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* CPU Features
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*/
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#define CONFIG_SYS_SC520_HIGH_SPEED 0
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#define CONFIG_SYS_SC520_RESET
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#define CONFIG_SYS_SC520_TIMER
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#undef CONFIG_SYS_GENERIC_TIMER
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#define CONFIG_SYS_PCAT_INTERRUPTS
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#define CONFIG_SYS_NUM_IRQS 16
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#define CONFIG_SYS_PC_BIOS
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#define CONFIG_SYS_PCI_BIOS
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#define CONFIG_SYS_X86_REALMODE
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#define CONFIG_SYS_X86_ISR_TIMER
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/*-----------------------------------------------------------------------
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* Memory organization:
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* 32kB Stack
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* 16kB Cache-As-RAM @ 0x19200000
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* 256kB Monitor
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* (128kB + Environment Sector Size) malloc pool
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*/
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#define CONFIG_SYS_STACK_SIZE (32 * 1024)
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#define CONFIG_SYS_CAR_ADDR 0x19200000
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#define CONFIG_SYS_CAR_SIZE (16 * 1024)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \
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128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*-----------------------------------------------------------------------
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* FLASH configuration
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* 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
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* 16MB StrataFlash #1 @ 0x10000000
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* 16MB StrataFlash #2 @ 0x11000000
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_FLASH_CFI_LEGACY
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_MAX_FLASH_BANKS 3
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#define CONFIG_SYS_FLASH_BASE 0x38000000
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#define CONFIG_SYS_FLASH_BASE_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE_2 0x11000000
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1, \
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CONFIG_SYS_FLASH_BASE_2}
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_SYS_FLASH_LEGACY_512Kx8
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#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
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/*-----------------------------------------------------------------------
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* Environment configuration
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* - Boot flash is 512kB with 64kB sectors
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* - StrataFlash is 32MB with 128kB sectors
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* - Redundant embedded environment is 25% of the Boot flash
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* - Redundant StrataFlash environment is <1% of the StrataFlash
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* - Environment is therefore located in StrataFlash
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* - Primary copy is located in first sector of first flash
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* - Redundant copy is located in second sector of first flash
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* - Stack is only 32kB, so environment size is limited to 4kB
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x01000
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#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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/*-----------------------------------------------------------------------
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* PCI configuration
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*/
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_SYS_FIRST_PCI_IRQ 10
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#define CONFIG_SYS_SECOND_PCI_IRQ 9
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#define CONFIG_SYS_THIRD_PCI_IRQ 11
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#define CONFIG_SYS_FORTH_PCI_IRQ 15
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/*-----------------------------------------------------------------------
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* Network device (TRL8100B) support
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*/
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#define CONFIG_RTL8139
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/*-----------------------------------------------------------------------
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* BOOTCS Control (for AM29LV040B-120JC)
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*
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* 000 0 00 0 000 11 0 011 }- 0x0033
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* \ / | \| | \ / \| | \ /
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* | | | | | | | |
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* | | | | | | | +---- 3 Wait States (First Access)
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* | | | | | | +------- Reserved
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* | | | | | +--------- 3 Wait States (Subsequent Access)
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* | | | | +------------- Reserved
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* | | | +---------------- Non-Paged Mode
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* | | +------------------ 8 Bit Wide
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* | +--------------------- GP Bus
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* +------------------------ Reserved
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*/
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#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
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/*-----------------------------------------------------------------------
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* ROMCS Control (for E28F128J3A-150 StrataFlash)
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*
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* 000 0 01 1 000 01 0 101 }- 0x0615
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* \ / | \| | \ / \| | \ /
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* | | | | | | | |
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* | | | | | | | +---- 5 Wait States (First Access)
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* | | | | | | +------- Reserved
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* | | | | | +--------- 1 Wait State (Subsequent Access)
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* | | | | +------------- Reserved
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* | | | +---------------- Paged Mode
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* | | +------------------ 16 Bit Wide
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* | +--------------------- GP Bus
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* +------------------------ Reserved
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*/
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#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
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#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
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/*-----------------------------------------------------------------------
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* SC520 General Purpose Bus configuration
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*
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* Chip Select Offset 1 Clock Cycle
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* Chip Select Pulse Width 8 Clock Cycles
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* Chip Select Read Offset 2 Clock Cycles
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* Chip Select Read Width 6 Clock Cycles
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* Chip Select Write Offset 2 Clock Cycles
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* Chip Select Write Width 6 Clock Cycles
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* Chip Select Recovery Time 2 Clock Cycles
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*
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* Timing Diagram (from SC520 Register Set Manual - Order #22005B)
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*
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* |<-------------General Purpose Bus Cycle---------------->|
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* | |
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* ----------------------\__________________/------------------
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* |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
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*
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* ------------------------\_______________/-------------------
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* |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
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*
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* --------------------------\_______________/-----------------
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* |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
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*
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* ________/-----------\_______________________________________
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* |<--->|<--------->|
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* ^ ^
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* (GPALEOFF + 1) |
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* |
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* (GPALEW + 1)
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*/
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#define CONFIG_SYS_SC520_GPCSOFF 0x00
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#define CONFIG_SYS_SC520_GPCSPW 0x07
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#define CONFIG_SYS_SC520_GPRDOFF 0x01
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#define CONFIG_SYS_SC520_GPRDW 0x05
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#define CONFIG_SYS_SC520_GPWROFF 0x01
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#define CONFIG_SYS_SC520_GPWRW 0x05
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#define CONFIG_SYS_SC520_GPCSRT 0x01
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/*-----------------------------------------------------------------------
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* SC520 Programmable I/O configuration
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*
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* Pin Mode Dir. Description
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* ----------------------------------------------------------------------
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* PIO0 PIO Output Unused
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* PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
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* PIO2 PIO Output Auxiliary power output enable
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* PIO3 GPAEN Output GP Bus Address Enable
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* PIO4 PIO Output Top Board Enable (active low)
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* PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
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* PIO6 PIO Input Data output of Power Supply ADC
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* PIO7 PIO Output Clock input to Power Supply ADC
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* PIO8 PIO Output Chip Select input of Power Supply ADC
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* PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
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* PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
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* PIO11 PIO Input StrataFlash 1 Status
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* PIO12 PIO Input StrataFlash 2 Status
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* PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
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* PIO14 PIO Input Low Input Voltage Warning (active low)
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* PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
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* PIO16 PIO Input Power Fail
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* PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
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* PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
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* PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
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* PIO20 GPIRQ3 Input UART D IRQ
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* PIO21 GPIRQ2 Input UART C IRQ
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* PIO22 GPIRQ1 Input UART B IRQ
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* PIO23 GPIRQ0 Input UART A IRQ
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* PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
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* PIO25 PIO Input Battery OK Indication
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* PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
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* PIO27 GPCS0# Output SRAM 1 Chip Select
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* PIO28 PIO Input Top Board UART CTS
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* PIO29 PIO Output FPGA Program Mode (active low)
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* PIO30 PIO Input FPGA Initialised (active low)
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* PIO31 PIO Input FPGA Done (active low)
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*/
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#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
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#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
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#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
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#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
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/*-----------------------------------------------------------------------
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* PIO Pin defines
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*/
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#define CONFIG_SYS_ENET_AUX_PWR 0x0004
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#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
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#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
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#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
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#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
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#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
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#define CONFIG_SYS_ENET_SF1_MODE 0x0200
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#define CONFIG_SYS_ENET_SF2_MODE 0x0400
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#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
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#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
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#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
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#define CONFIG_SYS_ENET_WATCHDOG 0x8000
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#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
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#define CONFIG_SYS_ENET_BAT_OK 0x0200
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#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
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#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
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#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
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#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
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|
|
|
/*-----------------------------------------------------------------------
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* Chip Select Pin Function Select
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*
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* 1 1 1 1 1 0 0 0 }- 0xf8
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* | | | | | | | |
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* | | | | | | | +--- Reserved
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* | | | | | | +----- GPCS1_SEL = ROMCS1#
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* | | | | | +------- GPCS2_SEL = ROMCS2#
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* | | | | +--------- GPCS3_SEL = GPCS3
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|
* | | | +----------- GPCS4_SEL = GPCS4
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* | | +------------- GPCS5_SEL = GPCS5
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* | +--------------- GPCS6_SEL = GPCS6
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* +----------------- GPCS7_SEL = GPCS7
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*/
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#define CONFIG_SYS_SC520_CSPFS 0xf8
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|
|
|
/*-----------------------------------------------------------------------
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|
* Clock Select (CLKTIMER[CLKTEST] pin)
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|
*
|
|
* 0 111 00 1 0 }- 0x72
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|
* | \ / \| | |
|
|
* | | | | +--- Pin Disabled
|
|
* | | | +----- Pin is an output
|
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* | | +------- Reserved
|
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* | +----------- Disabled (pin stays Low)
|
|
* +-------------- Reserved
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|
*/
|
|
#define CONFIG_SYS_SC520_CLKSEL 0x72
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|
|
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/*-----------------------------------------------------------------------
|
|
* Address Decode Control
|
|
*
|
|
* 0 00 0 0 0 0 0 }- 0x00
|
|
* | \| | | | | |
|
|
* | | | | | | +--- Integrated UART 1 is enabled
|
|
* | | | | | +----- Integrated UART 2 is enabled
|
|
* | | | | +------- Integrated RTC is enabled
|
|
* | | | +--------- Reserved
|
|
* | | +----------- I/O Hole accesses are forwarded to the external GP bus
|
|
* | +------------- Reserved
|
|
* +---------------- Write-protect violations do not generate an IRQ
|
|
*/
|
|
#define CONFIG_SYS_SC520_ADDDECCTL 0x00
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* UART Control
|
|
*
|
|
* 00000 1 1 1 }- 0x07
|
|
* \___/ | | |
|
|
* | | | +--- Transmit TC interrupt enable
|
|
* | | +----- Receive TC interrupt enable
|
|
* | +------- 1.8432 MHz
|
|
* +----------- Reserved
|
|
*/
|
|
#define CONFIG_SYS_SC520_UART1CTL 0x07
|
|
#define CONFIG_SYS_SC520_UART2CTL 0x07
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* System Arbiter Control
|
|
*
|
|
* 00000 1 1 0 }- 0x06
|
|
* \___/ | | |
|
|
* | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
|
|
* | | +----- The system arbiter operates in concurrent mode
|
|
* | +------- Park the PCI bus on the last master that acquired the bus
|
|
* +----------- Reserved
|
|
*/
|
|
#define CONFIG_SYS_SC520_SYSARBCTL 0x06
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* System Arbiter Master Enable
|
|
*
|
|
* 00000000000 0 0 0 1 1 }- 0x06
|
|
* \_________/ | | | | |
|
|
* | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
|
|
* | | | | +----- PCI master REQ1 enabled (Ethernet 2)
|
|
* | | | +------- PCI master REQ2 disabled
|
|
* | | +--------- PCI master REQ3 disabled
|
|
* | +----------- PCI master REQ4 disabled
|
|
* +------------------ Reserved
|
|
*/
|
|
#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* System Arbiter Master Enable
|
|
*
|
|
* 0 0000 0 00 0000 1 000 }- 0x06
|
|
* | \__/ | \| \__/ | \_/
|
|
* | | | | | | +---- Reserved
|
|
* | | | | | +------- Enable CPU-to-PCI bus write posting
|
|
* | | | | +---------- Reserved
|
|
* | | | +-------------- PCI bus reads to SDRAM are not automatically
|
|
* | | | retried
|
|
* | | +----------------- Target read FIFOs are not snooped during write
|
|
* | | transactions
|
|
* | +-------------------- Reserved
|
|
* +------------------------ Deassert the PCI bus reset signal
|
|
*/
|
|
#define CONFIG_SYS_SC520_HBCTL 0x08
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
|
|
* 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
|
|
* \ / | | | | \----+----/ \-----+------/
|
|
* | | | | | | +---------- Start at 0x38000000
|
|
* | | | | | +----------------------- 512kB Region Size
|
|
* | | | | | ((7 + 1) * 64kB)
|
|
* | | | | +------------------------------ 64kB Page Size
|
|
* | | | +-------------------------------- Writes Enabled (So it can be
|
|
* | | | reprogrammed!)
|
|
* | | +---------------------------------- Caching Disabled
|
|
* | +------------------------------------ Execution Enabled
|
|
* +--------------------------------------- BOOTCS
|
|
*/
|
|
#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Cache-As-RAM (Targets Boot Flash)
|
|
*
|
|
* 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
|
|
* \ / | | | | \--+--/ \-------+--------/
|
|
* | | | | | | +------------ Start at 0x19200000
|
|
* | | | | | +------------------------- 64k Region Size
|
|
* | | | | | ((15 + 1) * 4kB)
|
|
* | | | | +------------------------------ 4kB Page Size
|
|
* | | | +-------------------------------- Writes Enabled
|
|
* | | +---------------------------------- Caching Enabled
|
|
* | +------------------------------------ Execution Prevented
|
|
* +--------------------------------------- BOOTCS
|
|
*/
|
|
#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
|
|
*
|
|
* 001 110 0 000100000 0001000000000000 }- 0x38201000
|
|
* \ / \ / | \---+---/ \------+-------/
|
|
* | | | | +----------- Start at 0x00001000
|
|
* | | | +------------------------ 33 Bytes (0x20 + 1)
|
|
* | | +------------------------------ Ignored
|
|
* | +--------------------------------- GPCS6
|
|
* +------------------------------------- GP Bus I/O
|
|
*/
|
|
#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
|
|
* PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
|
|
*
|
|
* 010 101 0 0000000 100000000000000000 }- 0x54020000
|
|
* 010 111 0 0000000 100000000000000001 }- 0x5c020001
|
|
* \ / \ / | \--+--/ \-------+--------/
|
|
* | | | | +------------ Start at 0x200000000
|
|
* | | | | 0x200010000
|
|
* | | | +------------------------- 4kB Region Size
|
|
* | | | ((0 + 1) * 4kB)
|
|
* | | +------------------------------ 4k Page Size
|
|
* | +--------------------------------- GPCS5
|
|
* | GPCS7
|
|
* +------------------------------------- GP Bus Memory
|
|
*/
|
|
#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
|
|
#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
|
|
* PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
|
|
* PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
|
|
* PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
|
|
*
|
|
* 001 000 0 000000111 0001001111111000 }- 0x200713f8
|
|
* 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
|
|
* 001 011 0 000000111 0001001011111000 }- 0x300711f8
|
|
* 001 011 0 000000111 0001001011111000 }- 0x340710f8
|
|
* \ / \ / | \---+---/ \------+-------/
|
|
* | | | | +----------- Start at 0x013f8
|
|
* | | | | 0x012f8
|
|
* | | | | 0x011f8
|
|
* | | | | 0x010f8
|
|
* | | | +------------------------ 33 Bytes (32 + 1)
|
|
* | | +------------------------------ Ignored
|
|
* | +--------------------------------- GPCS6
|
|
* +------------------------------------- GP Bus I/O
|
|
*/
|
|
#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
|
|
#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
|
|
#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
|
|
#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
|
|
* PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
|
|
*
|
|
* 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
|
|
* 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
|
|
* \ / | | | | \----+----/ \-----+------/
|
|
* | | | | | | +---------- Start at 0x10000000
|
|
* | | | | | | 0x11000000
|
|
* | | | | | +----------------------- 16MB Region Size
|
|
* | | | | | ((255 + 1) * 64kB)
|
|
* | | | | +------------------------------ 64kB Page Size
|
|
* | | | +-------------------------------- Writes Enabled
|
|
* | | +---------------------------------- Caching Disabled
|
|
* | +------------------------------------ Execution Enabled
|
|
* +--------------------------------------- ROMCS1
|
|
* ROMCS2
|
|
*/
|
|
#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
|
|
#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
|
|
* PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
|
|
*
|
|
* 010 000 1 00000001111 01100100000000 }- 0x4203d900
|
|
* 010 011 1 00000001111 01100100010000 }- 0x4e03d910
|
|
* \ / \ / | \----+----/ \-----+------/
|
|
* | | | | +---------- Start at 0x19000000
|
|
* | | | | 0x19100000
|
|
* | | | +----------------------- 1MB Region Size
|
|
* | | | ((15 + 1) * 64kB)
|
|
* | | +------------------------------ 64kB Page Size
|
|
* | +--------------------------------- GPCS0
|
|
* | GPCS3
|
|
* +------------------------------------- GP Bus Memory
|
|
*/
|
|
#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
|
|
#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
|
|
*
|
|
* 010 100 0 00000000 11000000100000000 }- 0x50018100
|
|
* \ / \ / | \---+--/ \-------+-------/
|
|
* | | | | +----------- Start at 0x18100000
|
|
* | | | +------------------------ 4kB Region Size
|
|
* | | | ((0 + 1) * 4kB)
|
|
* | | +------------------------------ 4kB Page Size
|
|
* | +--------------------------------- GPCS4
|
|
* +------------------------------------- GP Bus Memory
|
|
*/
|
|
#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
|
|
|
|
#endif /* __CONFIG_H */
|
|
|