upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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187 lines
5.7 KiB
187 lines
5.7 KiB
/*
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* Copyright (C) 2004 by FS Forth-Systeme GmbH.
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* All rights reserved.
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* Markus Pietrek <mpietrek@fsforth.de>
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*
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* Configuation settings for the NetSilicon NS9750 DevBoard
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */
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#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */
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/* input clock of PLL */
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#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */
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#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2)
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#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
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#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
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/*@TODO #define CONFIG_STATUS_LED*/
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#define CONFIG_USE_IRQ
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_NS9750_UART 1 /* use on-chip UART */
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1 /* Port B */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 38400
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_PING
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#define CONFIG_BOOTDELAY 3
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/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
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#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.42.30
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#define CONFIG_SERVERIP 192.168.42.1
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/*#define CONFIG_BOOTFILE "elinos-lart" */
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/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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/* what's this ? it's not used anywhere */
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#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */
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#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */
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#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64)
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#define NS9750_ETH_PHY_ADDRESS (0x0000)
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/*-----------------------------------------------------------------------
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* Stack sizes
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*/
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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/* TODO */
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#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
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#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
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#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* @TODO*/
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#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
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#if 0
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#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
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#endif
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#ifdef CONFIG_AMD_LV800
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#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
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#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
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#endif
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#ifdef CONFIG_AMD_LV400
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#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
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#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
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#endif
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/* @TODO */
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/*#define CONFIG_ENV_IS_IN_FLASH 1*/
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#ifdef CONFIG_STATUS_LED
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extern void __led_init(led_id_t mask, int state);
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extern void __led_toggle(led_id_t mask);
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extern void __led_set(led_id_t mask, int state);
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#endif /* CONFIG_STATUS_LED */
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#endif /* __CONFIG_H */
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