upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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298 lines
9.1 KiB
298 lines
9.1 KiB
/*
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* (C) Copyright 2004
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* TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8220 1
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#define CONFIG_SORCERY 1 /* Sorcery board */
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#define CONFIG_SYS_TEXT_BASE 0xfff00000
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
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determine the CPU speed. */
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#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
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#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/* PCI */
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_MEM_BUS 0x80000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x71000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_PCI_CFG_BUS 0x70000000
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#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
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#define CONFIG_PCI_CFG_SIZE 0x01000000
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SNTP
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/*
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* Default Environment
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_HOSTNAME sorcery
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
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":$hostname:$netdev:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm $kernel_addr\0" \
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"flash_self=run ramargs addip;" \
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"bootm $kernel_addr $ramdisk_addr\0" \
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"net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/sorcery/uImage\0" \
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"kernel_addr=FFE00000\0" \
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"ramdisk_addr=FFB00000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_EEPRO100
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_MODULE 1
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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/*
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* Flexbus Chipselect configuration
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* Beware: Some CS# seem to be mandatory (if these CS# are not set,
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* board can hang-up in unpredictable place).
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* Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
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*/
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/* Flash */
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#define CONFIG_SYS_CS0_BASE 0xf800
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#define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
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#define CONFIG_SYS_CS0_CTRL 0x001019c0
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/* NVM */
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#define CONFIG_SYS_CS1_BASE 0xf7e8
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#define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
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#define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
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/* Atlas2 + Gemini */
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#define CONFIG_SYS_CS2_BASE 0xf7e7
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#define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
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#define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
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/* CAN Controller */
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#define CONFIG_SYS_CS3_BASE 0xf7e6
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#define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
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#define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
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/* Foreign interface */
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#define CONFIG_SYS_CS4_BASE 0xf7e5
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#define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
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#define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
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/* CPLD */
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#define CONFIG_SYS_CS5_BASE 0xf7e4
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#define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
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#define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
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#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
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#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
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#define CONFIG_ENV_SIZE 0x4000 /* 16K */
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_OVERWRITE 1
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#if defined CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_EEPROM
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#elif defined CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_EEPROM
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#elif defined CONFIG_ENV_IS_IN_EEPROM
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_FLASH
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#endif
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
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#define CONFIG_SYS_SRAM_SIZE 0x8000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/* SDRAM configuration (for SPD) */
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#define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
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#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
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#define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
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#define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
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/* SDRAM drive strength register (for SSTL_2 class II)*/
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#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
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(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
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(DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
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(DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
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(DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC8220_FEC 1
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#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
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#define CONFIG_PHY_ADDR 0x1F
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#define CONFIG_MII 1
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT 0
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#define CONFIG_SYS_HID0_FINAL 0
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/*
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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*/
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#endif /* __CONFIG_H */
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