upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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454 lines
13 KiB
454 lines
13 KiB
/*
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* (C) Copyright 2009-2012
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* Jens Scharsig <esw@bus-elekronik.de>
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* BuS Elektronik GmbH & Co. KG
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*
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* Configuation settings for the VL_MA2SC board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*--------------------------------------------------------------------------*/
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#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
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#define CONFIG_AT91FAMILY
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#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
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#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_MISC_INIT_R
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#include <asm/hardware.h>
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#define MACH_TYPE_VL_MA2SC 2412
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#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
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#define CONFIG_SYS_DCACHE_OFF
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#ifdef CONFIG_RAMLOAD
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#define CONFIG_SYS_TEXT_BASE 0x21000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
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#define CONFIG_IDENT_STRING " on MiS Activ 2"
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AT91_GPIO
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#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
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#define CONFIG_SYS_USE_NORFLASH
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#define CONFIG_SYS_USE_BOOT_NORFLASH
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#endif
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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/*
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* Hardware drivers
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*/
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_WATCHDOG
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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/* LCD */
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#define CONFIG_LCD
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#define CONFIG_ATMEL_LCD
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SYS_BLACK_ON_WHITE
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#define LCD_BPP LCD_COLOR8
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#define CONFIG_ATMEL_LCD_BGR555
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_LOADS
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#define CONFIG_CMD_BMP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_MD5SUM
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#define CONFIG_CMD_SHA1SUM
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/*
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#define CONFIG_CMD_SPI
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*/
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_USB
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_MD5
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#define CONFIG_SHA1
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/*----------------------------------------------------------------------------
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* Hardware confuguration
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*---------------------------------------------------------------------------*/
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE
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#define CONFIG_AT91C_PQFP_UHPBUG
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/* I2C-Bus */
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
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#ifndef CONFIG_HARD_I2C
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#define CONFIG_SOFT_I2C
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/* Software I2C driver configuration */
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#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
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#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
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#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
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#define I2C_INIT i2c_init_board();
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#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
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#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
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#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
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#define I2C_SDA(bit) \
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do { \
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if (bit) \
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writel(AT91_PIN_SDA, &pio->piob.sodr); \
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else \
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writel(AT91_PIN_SDA, &pio->piob.codr); \
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} while (0);
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#define I2C_SCL(bit) \
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do { \
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if (bit) \
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writel(AT91_PIN_SCL, &pio->piob.sodr); \
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else \
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writel(AT91_PIN_SCL, &pio->piob.codr); \
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} while (0);
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#endif
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/* I2C-RTC */
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1338
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#endif
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
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#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
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/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
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(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
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AT91_MATRIX_CSA_EBI_CS1A)
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/* user reset enable */
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#define CONFIG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_MR_URSTEN | \
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AT91_RSTC_MR_ERSTL(15))
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/* Disable Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
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AT91_WDT_MR_WDV(0xFFF) | \
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AT91_WDT_MR_WDDIS | \
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AT91_WDT_MR_WDD(0xFFF))
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/* clocks */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
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#define MHZ180
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#if defined(MHZ199)
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/* 199,8994 MHZ */
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#define MASTER_PLL_MUL 911
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#define MASTER_PLL_DIV 56
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#define MASTER_PLL_OUT 2
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#elif defined(MHZ180)
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/* 180 MHZ */
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#define MASTER_PLL_MUL 1875
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#define MASTER_PLL_DIV 128
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#define MASTER_PLL_OUT 2
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#elif defined(MHZTEST)
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/* Test MHZ */
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#define CONFIG_DISPLAY_CPUINFO
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#define MASTER_PLL_MUL 8
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#define MASTER_PLL_DIV 1
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#define MASTER_PLL_OUT 2
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#else
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/* 176.9472 MHZ */
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#define MASTER_PLL_MUL 72
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#define MASTER_PLL_DIV 5
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#define MASTER_PLL_OUT 2
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#endif
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLAR_29 | \
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AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
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AT91_PMC_PLLXR_PLLCOUNT(63) | \
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AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
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AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
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#define CONFIG_SYS_SDRC_MR_VAL1 0
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#define CONFIG_SYS_SDRC_TR_VAL1 700
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#define CONFIG_SYS_SDRC_CR_VAL \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_3 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(2 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(8 << 28)) /* Exit Self Refresh to Active Delay */
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#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* NOR flash */
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define PHYS_FLASH_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
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AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
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AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
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AT91_SMC_MODE_DBW_16 | \
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AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#endif
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_RETRY_COUNT 5
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x21e00000
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/* Address and size of Primary Environment Sector */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 0x20000
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#else
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
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38400, 57600, 9600 }
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN \
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ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
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#ifndef CONFIG_RAMLOAD
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#define CONFIG_BOOTCOMMAND "run nfsboot"
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#endif
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#define CONFIG_BOOT_RETRY_TIME -1
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#define CONFIG_BOOT_RETRY_MIN 15
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#define CONFIG_NFSBOOTCOMMAND \
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"dhcp $(copy_addr) $(kernelname);" \
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"run bootargsdefaults;" \
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"set bootargs $(bootargs) boot=nfs " \
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";echo $(bootargs)" \
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";bootm"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"ubootaddr=10000000\0" \
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"splashimage=10080000\0" \
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"kerneladdr=100A0000\0" \
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"kernelsize=00800000\0" \
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"minifsaddr=108A0000\0" \
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"minifssize=00060000\0" \
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"rootfsaddr=10900000\0" \
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"copy_addr=20200000\0" \
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"rootfssize=01700000\0" \
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"kernelname=uImage_vl_ma2sc\0" \
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"bootargsdefaults=set bootargs " \
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"console=ttyS0,115200 " \
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"video=atmel_lcdfb " \
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"mem=62M " \
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"panic=10 " \
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"boardrevison=\\\"${revision}\\\" " \
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"uboot=\\\"${ver}\\\" " \
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"\0" \
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"update_all=run update_kernel;run update_root;" \
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"run update_splash; run update_uboot\0" \
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"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
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"dhcp $(copy_addr) $(kernelname);" \
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"erase $(kerneladdr) +$(kernelsize);" \
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"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
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"protect on $(kerneladdr) +$(kernelsize)" \
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"\0" \
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"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
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"dhcp $(copy_addr) vl_ma2sc.root;" \
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"erase $(rootfsaddr) +$(rootfssize);" \
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"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
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"\0" \
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"update_splash=protect off $(splashimage) +20000;" \
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"dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
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"erase $(splashimage) +20000;" \
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"cp.b $(fileaddr) 10080000 $(filesize);" \
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"protect on $(splashimage) +20000\0" \
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"update_uboot=protect off 10000000 1005FFFF;" \
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"dhcp $(copy_addr) u-boot_vl_ma2sc;" \
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"erase 10000000 1005FFFF;" \
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"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
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"protect on 10000000 1005FFFF;reset\0" \
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"emergency=run bootargsdefaults;" \
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"set bootargs $(bootargs) root=initramfs boot=emergency " \
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";bootm $(kerneladdr)\0" \
|
|
"netemergency=run bootargsdefaults;" \
|
|
"dhcp $(copy_addr) $(kernelname);" \
|
|
"set bootargs $(bootargs) root=initramfs boot=emergency " \
|
|
";bootm $(copy_addr)\0" \
|
|
"norboot=run bootargsdefaults;" \
|
|
"set bootargs $(bootargs) root=initramfs boot=local quiet " \
|
|
";bootm $(kerneladdr)\0" \
|
|
"nandboot=run bootargsdefaults;" \
|
|
"set bootargs $(bootargs) root=initramfs boot=nand " \
|
|
";bootm $(kerneladdr)\0" \
|
|
"setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
|
|
"clearenv=protect off 10060000 1007FFFF;" \
|
|
"erase 10060000 1007FFFF;reset\0" \
|
|
" "
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|
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#endif
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