upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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265 lines
7.6 KiB
265 lines
7.6 KiB
/*
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ic/sc520.h>
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#include <net.h>
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#include <netdev.h>
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#ifdef CONFIG_HW_WATCHDOG
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#include <watchdog.h>
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#endif
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#include "hardware.h"
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DECLARE_GLOBAL_DATA_PTR;
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#undef SC520_CDP_DEBUG
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#ifdef SC520_CDP_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
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static void enet_timer_isr(void);
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static void enet_toggle_run_led(void);
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void init_sc520_enet (void)
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{
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/* Set CPU Speed to 100MHz */
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writeb(0x01, &sc520_mmcr->cpuctl);
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/* wait at least one millisecond */
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asm("movl $0x2000,%%ecx\n"
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"0: pushl %%ecx\n"
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"popl %%ecx\n"
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"loop 0b\n": : : "ecx");
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/* turn on the SDRAM write buffer */
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writeb(0x11, &sc520_mmcr->dbctl);
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/* turn on the cache and disable write through */
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asm("movl %%cr0, %%eax\n"
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"andl $0x9fffffff, %%eax\n"
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"movl %%eax, %%cr0\n" : : : "eax");
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}
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/*
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* Miscellaneous platform dependent initializations
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*/
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int board_early_init_f(void)
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{
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init_sc520_enet();
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writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
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writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
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writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
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writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
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writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
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writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
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writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
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writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
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writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
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writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
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writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
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writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
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writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
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writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
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writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
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writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
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writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
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writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
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writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
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writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
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writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
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writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
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writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
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writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
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writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
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writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
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/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
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/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
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/* Disable Watchdog */
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writew(0x3333, &sc520_mmcr->wdtmrctl);
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writew(0xcccc, &sc520_mmcr->wdtmrctl);
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writew(0x0000, &sc520_mmcr->wdtmrctl);
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/* Chip Select Configuration */
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writew(0x0033, &sc520_mmcr->bootcsctl);
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writew(0x0615, &sc520_mmcr->romcs1ctl);
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writew(0x0615, &sc520_mmcr->romcs2ctl);
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writeb(0x00, &sc520_mmcr->adddecctl);
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writeb(0x07, &sc520_mmcr->uart1ctl);
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writeb(0x07, &sc520_mmcr->uart2ctl);
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writeb(0x06, &sc520_mmcr->sysarbctl);
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writew(0x0003, &sc520_mmcr->sysarbmenb);
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return 0;
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}
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int board_early_init_r(void)
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{
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/* CPU Speed to 100MHz */
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gd->cpu_clk = 100000000;
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/* Crystal is 33.000MHz */
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gd->bus_clk = 33000000;
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return 0;
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}
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int dram_init(void)
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{
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init_sc520_dram();
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return 0;
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}
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void show_boot_progress(int val)
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{
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uchar led_mask;
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led_mask = 0x00;
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if (val < 0)
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led_mask |= LED_ERR_BITMASK;
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led_mask |= (uchar)(val & 0x001f);
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outb(led_mask, LED_LATCH_ADDRESS);
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}
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int last_stage_init(void)
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{
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int minor;
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int major;
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major = minor = 0;
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outb(0x00, LED_LATCH_ADDRESS);
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register_timer_isr (enet_timer_isr);
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printf("Serck Controls eNET\n");
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return 0;
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}
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void setup_pcat_compatibility()
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{
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/* disable global interrupt mode */
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writeb(0x40, &sc520_mmcr->picicr);
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/* set all irqs to edge */
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writeb(0x00, &sc520_mmcr->pic_mode[0]);
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writeb(0x00, &sc520_mmcr->pic_mode[1]);
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writeb(0x00, &sc520_mmcr->pic_mode[2]);
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/*
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* active low polarity on PIC interrupt pins,
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* active high polarity on all other irq pins
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*/
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writew(0x0000,&sc520_mmcr->intpinpol);
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/* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
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writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
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writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
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writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
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/* Disable all other interrupt sources */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
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}
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void enet_timer_isr(void)
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{
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static long enet_ticks = 0;
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enet_ticks++;
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/* Toggle Watchdog every 100ms */
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if ((enet_ticks % 100) == 0)
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hw_watchdog_reset();
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/* Toggle Run LED every 500ms */
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if ((enet_ticks % 500) == 0)
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enet_toggle_run_led();
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}
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void hw_watchdog_reset(void)
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{
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/* Watchdog Reset must be atomic */
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long flag = disable_interrupts();
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if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
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sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
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else
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sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
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if (flag)
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enable_interrupts();
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}
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void enet_toggle_run_led(void)
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{
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unsigned char leds_state= inb(LED_LATCH_ADDRESS);
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if (leds_state & LED_RUN_BITMASK)
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outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
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else
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outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
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}
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