upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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532 lines
15 KiB
532 lines
15 KiB
/*
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* Copyright 2007-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
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*
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* Initialize controller and call the common driver/pci pci_hose_scan to
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* scan for bridges and devices.
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*
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* Hose fields which need to be pre-initialized by board specific code:
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* regions[]
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* first_busno
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*
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* Fields updated:
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* last_busno
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*/
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/fsl_pci.h>
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/* Freescale-specific PCI config registers */
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#define FSL_PCI_PBFR 0x44
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#define FSL_PCIE_CAP_ID 0x4c
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#define FSL_PCIE_CFG_RDY 0x4b0
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#define FSL_PROG_IF_AGENT 0x1
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void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus);
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void pciauto_postscan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus);
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void pciauto_config_init(struct pci_controller *hose);
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#ifndef CONFIG_SYS_PCI_MEMORY_BUS
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#define CONFIG_SYS_PCI_MEMORY_BUS 0
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0
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#endif
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#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
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#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
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#endif
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/* Setup one inbound ATMU window.
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*
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* We let the caller decide what the window size should be
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*/
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static void set_inbound_window(volatile pit_t *pi,
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struct pci_region *r,
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u64 size)
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{
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u32 sz = (__ilog2_u64(size) - 1);
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u32 flag = PIWAR_EN | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
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out_be32(&pi->pitar, r->phys_start >> 12);
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out_be32(&pi->piwbar, r->bus_start >> 12);
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#ifdef CONFIG_SYS_PCI_64BIT
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out_be32(&pi->piwbear, r->bus_start >> 44);
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#else
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out_be32(&pi->piwbear, 0);
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#endif
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if (r->flags & PCI_REGION_PREFETCH)
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flag |= PIWAR_PF;
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out_be32(&pi->piwar, flag | sz);
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}
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int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
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pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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return fsl_is_pci_agent(hose);
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}
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static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
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u64 out_lo, u8 pcie_cap,
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volatile pit_t *pi)
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{
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struct pci_region *r = hose->regions + hose->region_count;
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u64 sz = min((u64)gd->ram_size, (1ull << 32));
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phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
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pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
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pci_size_t pci_sz;
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/* we have no space available for inbound memory mapping */
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if (bus_start > out_lo) {
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printf ("no space for inbound mapping of memory\n");
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return 0;
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}
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/* limit size */
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if ((bus_start + sz) > out_lo) {
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sz = out_lo - bus_start;
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debug ("limiting size to %llx\n", sz);
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}
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pci_sz = 1ull << __ilog2_u64(sz);
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/*
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* we can overlap inbound/outbound windows on PCI-E since RX & TX
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* links a separate
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*/
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if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
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debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)bus_start, (u64)phys_start, (u64)sz);
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pci_set_region(r, bus_start, phys_start, sz,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
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PCI_REGION_PREFETCH);
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/* if we aren't an exact power of two match, pci_sz is smaller
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* round it up to the next power of two. We report the actual
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* size to pci region tracking.
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*/
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if (pci_sz != sz)
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sz = 2ull << __ilog2_u64(sz);
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set_inbound_window(pi--, r++, sz);
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sz = 0; /* make sure we dont set the R2 window */
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} else {
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debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)bus_start, (u64)phys_start, (u64)pci_sz);
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pci_set_region(r, bus_start, phys_start, pci_sz,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
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PCI_REGION_PREFETCH);
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set_inbound_window(pi--, r++, pci_sz);
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sz -= pci_sz;
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bus_start += pci_sz;
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phys_start += pci_sz;
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pci_sz = 1ull << __ilog2_u64(sz);
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if (sz) {
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debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)bus_start, (u64)phys_start, (u64)pci_sz);
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pci_set_region(r, bus_start, phys_start, pci_sz,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
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PCI_REGION_PREFETCH);
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set_inbound_window(pi--, r++, pci_sz);
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sz -= pci_sz;
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bus_start += pci_sz;
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phys_start += pci_sz;
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}
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}
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#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
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/*
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* On 64-bit capable systems, set up a mapping for all of DRAM
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* in high pci address space.
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*/
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pci_sz = 1ull << __ilog2_u64(gd->ram_size);
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/* round up to the next largest power of two */
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if (gd->ram_size > pci_sz)
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pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
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debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
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(u64)CONFIG_SYS_PCI_MEMORY_PHYS,
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(u64)pci_sz);
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pci_set_region(r,
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CONFIG_SYS_PCI64_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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pci_sz,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
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PCI_REGION_PREFETCH);
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set_inbound_window(pi--, r++, pci_sz);
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#else
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pci_sz = 1ull << __ilog2_u64(sz);
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if (sz) {
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debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)bus_start, (u64)phys_start, (u64)pci_sz);
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pci_set_region(r, bus_start, phys_start, pci_sz,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
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PCI_REGION_PREFETCH);
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sz -= pci_sz;
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bus_start += pci_sz;
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phys_start += pci_sz;
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set_inbound_window(pi--, r++, pci_sz);
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}
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#endif
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#ifdef CONFIG_PHYS_64BIT
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if (sz && (((u64)gd->ram_size) < (1ull << 32)))
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printf("Was not able to map all of memory via "
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"inbound windows -- %lld remaining\n", sz);
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#endif
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hose->region_count = r - hose->regions;
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return 1;
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}
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void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
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{
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u16 temp16;
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u32 temp32;
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int enabled, r, inbound = 0;
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u16 ltssm;
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u8 temp8, pcie_cap;
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
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struct pci_region *reg = hose->regions + hose->region_count;
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pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
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/* Initialize ATMU registers based on hose regions and flags */
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volatile pot_t *po = &pci->pot[1]; /* skip 0 */
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volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */
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u64 out_hi = 0, out_lo = -1ULL;
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u32 pcicsrbar, pcicsrbar_sz;
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#ifdef DEBUG
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int neg_link_w;
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#endif
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pci_setup_indirect(hose, cfg_addr, cfg_data);
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/* Handle setup of outbound windows first */
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for (r = 0; r < hose->region_count; r++) {
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unsigned long flags = hose->regions[r].flags;
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u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
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flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
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if (flags != PCI_REGION_SYS_MEMORY) {
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u64 start = hose->regions[r].bus_start;
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u64 end = start + hose->regions[r].size;
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out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
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out_be32(&po->potar, start >> 12);
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#ifdef CONFIG_SYS_PCI_64BIT
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out_be32(&po->potear, start >> 44);
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#else
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out_be32(&po->potear, 0);
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#endif
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if (hose->regions[r].flags & PCI_REGION_IO) {
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out_be32(&po->powar, POWAR_EN | sz |
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POWAR_IO_READ | POWAR_IO_WRITE);
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} else {
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out_be32(&po->powar, POWAR_EN | sz |
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POWAR_MEM_READ | POWAR_MEM_WRITE);
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out_lo = min(start, out_lo);
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out_hi = max(end, out_hi);
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}
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po++;
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}
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}
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debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
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/* setup PCSRBAR/PEXCSRBAR */
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
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pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
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pcicsrbar_sz = ~pcicsrbar_sz + 1;
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if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
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(out_lo > 0x100000000ull))
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pcicsrbar = 0x100000000ull - pcicsrbar_sz;
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else
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pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
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out_lo = min(out_lo, (u64)pcicsrbar);
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debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
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pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
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pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
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hose->region_count++;
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/* see if we are a PCIe or PCI controller */
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pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
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/* inbound */
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inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
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for (r = 0; r < hose->region_count; r++)
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debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
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(u64)hose->regions[r].phys_start,
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hose->regions[r].bus_start,
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hose->regions[r].size,
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hose->regions[r].flags);
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pci_register_hose(hose);
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pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
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hose->current_busno = hose->first_busno;
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out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
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out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
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* - Master abort (pci)
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* - Master PERR (pci)
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* - ICCA (PCIe)
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*/
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pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
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temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
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pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
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if (pcie_cap == PCI_CAP_ID_EXP) {
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pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
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enabled = ltssm >= PCI_LTSSM_L0;
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#ifdef CONFIG_FSL_PCIE_RESET
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if (ltssm == 1) {
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int i;
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debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
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/* assert PCIe reset */
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setbits_be32(&pci->pdb_stat, 0x08000000);
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(void) in_be32(&pci->pdb_stat);
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udelay(100);
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debug(" Asserting PCIe reset @%x = %x\n",
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&pci->pdb_stat, in_be32(&pci->pdb_stat));
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/* clear PCIe reset */
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clrbits_be32(&pci->pdb_stat, 0x08000000);
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asm("sync;isync");
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for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
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pci_hose_read_config_word(hose, dev, PCI_LTSSM,
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<ssm);
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udelay(1000);
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debug("....PCIe link error. "
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"LTSSM=0x%02x.\n", ltssm);
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}
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enabled = ltssm >= PCI_LTSSM_L0;
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/* we need to re-write the bar0 since a reset will
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* clear it
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*/
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pci_hose_write_config_dword(hose, dev,
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PCI_BASE_ADDRESS_0, pcicsrbar);
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}
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#endif
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if (!enabled) {
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debug("....PCIE link error. Skipping scan."
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"LTSSM=0x%02x\n", ltssm);
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hose->last_busno = hose->first_busno;
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return;
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}
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out_be32(&pci->pme_msg_det, 0xffffffff);
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out_be32(&pci->pme_msg_int_en, 0xffffffff);
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#ifdef DEBUG
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pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
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neg_link_w = (temp16 & 0x3f0 ) >> 4;
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printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
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ltssm, neg_link_w);
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#endif
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hose->current_busno++; /* Start scan with secondary */
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pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
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}
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/* Use generic setup_device to initialize standard pci regs,
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* but do not allocate any windows since any BAR found (such
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* as PCSRBAR) is not in this cpu's memory space.
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*/
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pciauto_setup_device(hose, dev, 0, hose->pci_mem,
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hose->pci_prefetch, hose->pci_io);
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if (inbound) {
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
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pci_hose_write_config_word(hose, dev, PCI_COMMAND,
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temp16 | PCI_COMMAND_MEMORY);
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}
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#ifndef CONFIG_PCI_NOSCAN
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pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
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/* Programming Interface (PCI_CLASS_PROG)
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* 0 == pci host or pcie root-complex,
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* 1 == pci agent or pcie end-point
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*/
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if (!temp8) {
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printf(" Scanning PCI bus %02x\n",
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hose->current_busno);
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hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
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} else {
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debug(" Not scanning PCI bus %02x. PI=%x\n",
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hose->current_busno, temp8);
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hose->last_busno = hose->current_busno;
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}
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/* if we are PCIe - update limit regs and subordinate busno
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* for the virtual P2P bridge
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*/
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if (pcie_cap == PCI_CAP_ID_EXP) {
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pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
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}
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#else
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hose->last_busno = hose->current_busno;
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#endif
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/* Clear all error indications */
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if (pcie_cap == PCI_CAP_ID_EXP)
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out_be32(&pci->pme_msg_det, 0xffffffff);
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out_be32(&pci->pedr, 0xffffffff);
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pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
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if (temp16) {
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pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
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}
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pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
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if (temp16) {
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pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
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}
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}
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int fsl_is_pci_agent(struct pci_controller *hose)
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{
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u8 prog_if;
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pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
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return (prog_if == FSL_PROG_IF_AGENT);
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}
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int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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struct pci_controller *hose, int busno)
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{
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volatile ccsr_fsl_pci_t *pci;
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|
struct pci_region *r;
|
|
|
|
pci = (ccsr_fsl_pci_t *) pci_info->regs;
|
|
|
|
/* on non-PCIe controllers we don't have pme_msg_det so this code
|
|
* should do nothing since the read will return 0
|
|
*/
|
|
if (in_be32(&pci->pme_msg_det)) {
|
|
out_be32(&pci->pme_msg_det, 0xffffffff);
|
|
debug (" with errors. Clearing. Now 0x%08x",
|
|
pci->pme_msg_det);
|
|
}
|
|
|
|
r = hose->regions + hose->region_count;
|
|
|
|
/* outbound memory */
|
|
pci_set_region(r++,
|
|
pci_info->mem_bus,
|
|
pci_info->mem_phys,
|
|
pci_info->mem_size,
|
|
PCI_REGION_MEM);
|
|
|
|
/* outbound io */
|
|
pci_set_region(r++,
|
|
pci_info->io_bus,
|
|
pci_info->io_phys,
|
|
pci_info->io_size,
|
|
PCI_REGION_IO);
|
|
|
|
hose->region_count = r - hose->regions;
|
|
hose->first_busno = busno;
|
|
|
|
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
|
|
|
|
if (fsl_is_pci_agent(hose)) {
|
|
fsl_pci_config_unlock(hose);
|
|
hose->last_busno = hose->first_busno;
|
|
}
|
|
|
|
printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
|
|
hose->first_busno, hose->last_busno);
|
|
|
|
return(hose->last_busno + 1);
|
|
}
|
|
|
|
/* Enable inbound PCI config cycles for agent/endpoint interface */
|
|
void fsl_pci_config_unlock(struct pci_controller *hose)
|
|
{
|
|
pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
|
|
u8 agent;
|
|
u8 pcie_cap;
|
|
u16 pbfr;
|
|
|
|
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
|
|
if (!agent)
|
|
return;
|
|
|
|
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
|
|
if (pcie_cap != 0x0) {
|
|
/* PCIe - set CFG_READY bit of Configuration Ready Register */
|
|
pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
|
|
} else {
|
|
/* PCI - clear ACL bit of PBFR */
|
|
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
|
|
pbfr &= ~0x20;
|
|
pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
#include <libfdt.h>
|
|
#include <fdt_support.h>
|
|
|
|
void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
|
struct pci_controller *hose)
|
|
{
|
|
int off = fdt_path_offset(blob, pci_alias);
|
|
u32 bus_range[2];
|
|
|
|
if (off < 0)
|
|
return;
|
|
|
|
/* We assume a cfg_addr not being set means we didn't setup the controller */
|
|
if ((hose == NULL) || (hose->cfg_addr == NULL)) {
|
|
fdt_del_node_and_alias(blob, pci_alias);
|
|
} else {
|
|
bus_range[0] = 0;
|
|
bus_range[1] = hose->last_busno - hose->first_busno;
|
|
fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
|
|
fdt_pci_dma_ranges(blob, off, hose);
|
|
}
|
|
}
|
|
#endif
|
|
|