upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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239 lines
5.9 KiB
239 lines
5.9 KiB
/*
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* SuperH SCIF device driver.
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* Copyright (c) 2007,2008 Nobuhiro Iwamatsu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#if defined(CONFIG_CONS_SCIF0)
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# define SCIF_BASE SCIF0_BASE
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#elif defined(CONFIG_CONS_SCIF1)
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# define SCIF_BASE SCIF1_BASE
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#elif defined(CONFIG_CONS_SCIF2)
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# define SCIF_BASE SCIF2_BASE
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#elif defined(CONFIG_CONS_SCIF3)
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# define SCIF_BASE SCIF3_BASE
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#elif defined(CONFIG_CONS_SCIF4)
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# define SCIF_BASE SCIF4_BASE
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#elif defined(CONFIG_CONS_SCIF5)
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# define SCIF_BASE SCIF5_BASE
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#else
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# error "Default SCIF doesn't set....."
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#endif
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/* Base register */
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#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
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#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
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#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
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#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
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#if defined(CONFIG_CPU_SH7720) || \
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(defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A))
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# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
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# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
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# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
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#else
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# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
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# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
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# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
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#endif
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#if defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7785)
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# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
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# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0xFF
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#elif defined(CONFIG_CPU_SH7763)
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# if defined(CONFIG_CONS_SCIF2)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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# else
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# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
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# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0xFF
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# endif
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#elif defined(CONFIG_CPU_SH7723)
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# if defined(CONFIG_SCIF_A)
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# define SCLSR SCFSR
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# define LSR_ORER 0x0200
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# define FIFOLEVEL_MASK 0x3F
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#else
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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#endif
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#elif defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7722) || \
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defined(CONFIG_CPU_SH7203)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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#elif defined(CONFIG_CPU_SH7720)
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# define SCLSR SCFSR
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# define LSR_ORER 0x0200
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# define FIFOLEVEL_MASK 0x1F
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#elif defined(CONFIG_CPU_SH7710) || \
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defined(CONFIG_CPU_SH7712)
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# define SCLSR SCFSR /* SCSSR */
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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#endif
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/* SCBRR register value setting */
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#if defined(CONFIG_CPU_SH7720)
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# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1)
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#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
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/* SH7723 SCIFA use bus clock. So clock *2 */
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# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1)
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#else /* Generic SuperH */
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# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1)
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#endif
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#define SCR_RE (1 << 4)
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#define SCR_TE (1 << 5)
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#define FCR_RFRST (1 << 1) /* RFCL */
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#define FCR_TFRST (1 << 2) /* TFCL */
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#define FSR_DR (1 << 0)
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#define FSR_RDF (1 << 1)
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#define FSR_FER (1 << 3)
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#define FSR_BRK (1 << 4)
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#define FSR_FER (1 << 3)
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#define FSR_TEND (1 << 6)
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#define FSR_ER (1 << 7)
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/*----------------------------------------------------------------------*/
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void serial_setbrg(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR);
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}
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int serial_init(void)
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{
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writew((SCR_RE | SCR_TE), SCSCR);
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writew(0, SCSMR);
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writew(0, SCSMR);
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writew((FCR_RFRST | FCR_TFRST), SCFCR);
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readw(SCFCR);
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writew(0, SCFCR);
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serial_setbrg();
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return 0;
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}
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static int serial_rx_fifo_level(void)
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{
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#if defined(SCRFDR)
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return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK;
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#else
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return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK;
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#endif
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}
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void serial_raw_putc(const char c)
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{
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unsigned int fsr_bits_to_clear;
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while (1) {
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if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */
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fsr_bits_to_clear = FSR_TEND;
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break;
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}
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}
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writeb(c, SCFTDR);
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if (fsr_bits_to_clear != 0)
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writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR);
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}
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void serial_putc(const char c)
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{
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if (c == '\n')
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serial_raw_putc('\r');
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serial_raw_putc(c);
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}
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void serial_puts(const char *s)
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{
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char c;
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while ((c = *s++) != 0)
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serial_putc(c);
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}
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int serial_tstc(void)
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{
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return serial_rx_fifo_level() ? 1 : 0;
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}
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#define FSR_ERR_CLEAR 0x0063
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#define RDRF_CLEAR 0x00fc
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void handle_error(void)
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{
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readw(SCFSR);
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writew(FSR_ERR_CLEAR, SCFSR);
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readw(SCLSR);
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writew(0x00, SCLSR);
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}
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int serial_getc_check(void)
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{
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unsigned short status;
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status = readw(SCFSR);
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if (status & (FSR_FER | FSR_ER | FSR_BRK))
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handle_error();
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if (readw(SCLSR) & LSR_ORER)
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handle_error();
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return status & (FSR_DR | FSR_RDF);
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}
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int serial_getc(void)
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{
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unsigned short status;
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char ch;
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while (!serial_getc_check())
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;
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ch = readb(SCFRDR);
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status = readw(SCFSR);
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writew(RDRF_CLEAR, SCFSR);
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if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
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handle_error();
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if (readw(SCLSR) & LSR_ORER)
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handle_error();
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return ch;
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}
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