upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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275 lines
7.6 KiB
275 lines
7.6 KiB
/*
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
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/ {
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soc {
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pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32h743-pinctrl";
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ranges = <0 0x58020000 0x3000>;
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pins-are-numbered;
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gpioa: gpio@58020000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x0 0x400>;
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clocks = <&rcc GPIOA_CK>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@58020400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x400 0x400>;
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clocks = <&rcc GPIOB_CK>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@58020800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x800 0x400>;
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clocks = <&rcc GPIOC_CK>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@58020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0xc00 0x400>;
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clocks = <&rcc GPIOD_CK>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@58021000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1000 0x400>;
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clocks = <&rcc GPIOE_CK>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@58021400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1400 0x400>;
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clocks = <&rcc GPIOF_CK>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@58021800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1800 0x400>;
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clocks = <&rcc GPIOG_CK>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@58021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1c00 0x400>;
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clocks = <&rcc GPIOH_CK>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@58022000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2000 0x400>;
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clocks = <&rcc GPIOI_CK>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@58022400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2400 0x400>;
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clocks = <&rcc GPIOJ_CK>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@58022800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2800 0x400>;
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clocks = <&rcc GPIOK_CK>;
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st,bank-name = "GPIOK";
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};
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usart1_pins: usart1@0 {
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pins1 {
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pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
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bias-disable;
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};
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};
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usart2_pins: usart2@0 {
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pins1 {
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pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
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bias-disable;
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};
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};
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
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<STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
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<STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
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<STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
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<STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
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<STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
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<STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
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<STM32H7_PE0_FUNC_FMC_NBL0>,
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<STM32H7_PE1_FUNC_FMC_NBL1>,
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<STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
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<STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
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<STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
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<STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
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<STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
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<STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
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<STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
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<STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
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<STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
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<STM32H7_PF0_FUNC_FMC_A0>,
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<STM32H7_PF1_FUNC_FMC_A1>,
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<STM32H7_PF2_FUNC_FMC_A2>,
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<STM32H7_PF3_FUNC_FMC_A3>,
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<STM32H7_PF4_FUNC_FMC_A4>,
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<STM32H7_PF5_FUNC_FMC_A5>,
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<STM32H7_PF11_FUNC_FMC_SDNRAS>,
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<STM32H7_PF12_FUNC_FMC_A6>,
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<STM32H7_PF13_FUNC_FMC_A7>,
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<STM32H7_PF14_FUNC_FMC_A8>,
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<STM32H7_PF15_FUNC_FMC_A9>,
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<STM32H7_PG0_FUNC_FMC_A10>,
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<STM32H7_PG1_FUNC_FMC_A11>,
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<STM32H7_PG2_FUNC_FMC_A12>,
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<STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
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<STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
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<STM32H7_PG8_FUNC_FMC_SDCLK>,
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<STM32H7_PG15_FUNC_FMC_SDNCAS>,
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<STM32H7_PH5_FUNC_FMC_SDNWE>,
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<STM32H7_PH6_FUNC_FMC_SDNE1>,
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<STM32H7_PH7_FUNC_FMC_SDCKE1>,
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<STM32H7_PH8_FUNC_FMC_D16>,
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<STM32H7_PH9_FUNC_FMC_D17>,
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<STM32H7_PH10_FUNC_FMC_D18>,
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<STM32H7_PH11_FUNC_FMC_D19>,
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<STM32H7_PH12_FUNC_FMC_D20>,
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<STM32H7_PH13_FUNC_FMC_D21>,
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<STM32H7_PH14_FUNC_FMC_D22>,
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<STM32H7_PH15_FUNC_FMC_D23>,
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<STM32H7_PI0_FUNC_FMC_D24>,
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<STM32H7_PI1_FUNC_FMC_D25>,
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<STM32H7_PI2_FUNC_FMC_D26>,
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<STM32H7_PI3_FUNC_FMC_D27>,
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<STM32H7_PI4_FUNC_FMC_NBL2>,
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<STM32H7_PI5_FUNC_FMC_NBL3>,
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<STM32H7_PI6_FUNC_FMC_D28>,
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<STM32H7_PI7_FUNC_FMC_D29>,
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<STM32H7_PI9_FUNC_FMC_D30>,
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<STM32H7_PI10_FUNC_FMC_D31>;
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slew-rate = <3>;
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};
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};
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sdmmc1_pins: sdmmc@0 {
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pins {
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pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
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<STM32H7_PC9_FUNC_SDMMC1_D1>,
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<STM32H7_PC10_FUNC_SDMMC1_D2>,
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<STM32H7_PC11_FUNC_SDMMC1_D3>,
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<STM32H7_PC12_FUNC_SDMMC1_CK>,
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<STM32H7_PD2_FUNC_SDMMC1_CMD>;
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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};
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pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
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pins {
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pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
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<STM32H7_PB9_FUNC_SDMMC1_CDIR>,
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<STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
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<STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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};
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};
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};
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