upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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151 lines
4.4 KiB
151 lines
4.4 KiB
/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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#include "pinmux-config-cardhu.h"
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#include <asm/arch/clock.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pmu.h>
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#include <asm/arch/sdmmc.h>
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#include <asm/arch-tegra/mmc.h>
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#include <asm/arch-tegra/tegra_mmc.h>
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#include <mmc.h>
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#include <i2c.h>
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_table(tegra3_pinmux_common,
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ARRAY_SIZE(tegra3_pinmux_common));
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pinmux_config_table(unused_pins_lowpower,
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ARRAY_SIZE(unused_pins_lowpower));
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}
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#if defined(CONFIG_MMC)
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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static void pin_mux_mmc(void)
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{
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}
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/* Do I2C/PMU writes to bring up SD card bus power */
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static void board_sdmmc_voltage_init(void)
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{
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uchar reg, data_buffer[1];
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int i;
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i2c_set_bus_num(0); /* PMU is on bus 0 */
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data_buffer[0] = 0x65;
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reg = 0x32;
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for (i = 0; i < MAX_I2C_RETRY; ++i) {
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if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
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udelay(100);
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}
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data_buffer[0] = 0x09;
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reg = 0x67;
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for (i = 0; i < MAX_I2C_RETRY; ++i) {
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if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
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udelay(100);
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}
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}
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static void pad_init_mmc(struct tegra_mmc *reg)
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{
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struct apb_misc_gp_ctlr *const gpc =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
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u32 val, offset = (unsigned int)reg;
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u32 padcfg, padmask;
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debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
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/* Set the pad drive strength for SDMMC1 or 3 only */
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if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
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debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
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__func__);
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return;
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}
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/* Set pads as per T30 TRM, section 24.6.1.2 */
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padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
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GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
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padmask = 0x00000FFF;
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if (offset == TEGRA_SDMMC1_BASE) {
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val = readl(&gpc->sdio1cfg);
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val &= padmask;
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val |= padcfg;
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writel(val, &gpc->sdio1cfg);
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} else { /* SDMMC3 */
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val = readl(&gpc->sdio3cfg);
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val &= padmask;
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val |= padcfg;
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writel(val, &gpc->sdio3cfg);
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}
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val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
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val &= 0xFFFFFFF0;
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val |= MEMCOMP_PADCTRL_VREF;
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writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
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val = readl(&sdmmc->sdmmc_auto_cal_config);
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val &= 0xFFFF0000;
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val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
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writel(val, &sdmmc->sdmmc_auto_cal_config);
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}
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("board_mmc_init called\n");
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/* Turn on SD-card bus power */
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board_sdmmc_voltage_init();
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/* Set up the SDMMC pads as per the TRM */
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pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
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/* Enable muxes, etc. for SDMMC controllers */
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pin_mux_mmc();
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/* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
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tegra_mmc_init(0, 8, -1, -1);
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/* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
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tegra_mmc_init(1, 8, -1, -1);
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return 0;
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}
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#endif /* MMC */
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