upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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229 lines
5.1 KiB
229 lines
5.1 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2017 Microchip Technology Inc. All rights reserved.
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*/
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#include <console.h>
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#include <watchdog.h>
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/* USB Vendor Requests */
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#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
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#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
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#define USB_VENDOR_REQUEST_GET_STATS 0xA2
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/* Tx Command A */
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#define TX_CMD_A_FCS BIT(22)
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#define TX_CMD_A_LEN_MASK 0x000FFFFF
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/* Rx Command A */
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#define RX_CMD_A_RXE BIT(18)
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#define RX_CMD_A_LEN_MASK 0x00003FFF
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/* SCSRs */
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#define ID_REV 0x00
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#define ID_REV_CHIP_ID_MASK 0xFFFF0000
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#define ID_REV_CHIP_ID_7500 0x7500
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#define ID_REV_CHIP_ID_7800 0x7800
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#define ID_REV_CHIP_ID_7850 0x7850
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#define INT_STS 0x0C
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#define HW_CFG 0x010
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#define HW_CFG_LRST BIT(1)
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#define PMT_CTL 0x014
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#define PMT_CTL_PHY_PWRUP BIT(10)
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#define PMT_CTL_READY BIT(7)
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#define PMT_CTL_PHY_RST BIT(4)
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#define E2P_CMD 0x040
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#define E2P_CMD_EPC_BUSY BIT(31)
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#define E2P_CMD_EPC_CMD_READ 0x00000000
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#define E2P_CMD_EPC_TIMEOUT BIT(10)
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#define E2P_CMD_EPC_ADDR_MASK 0x000001FF
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#define E2P_DATA 0x044
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#define RFE_CTL_BCAST_EN BIT(10)
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#define RFE_CTL_DA_PERFECT BIT(1)
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#define FCT_RX_CTL_EN BIT(31)
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#define FCT_TX_CTL_EN BIT(31)
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#define MAC_CR 0x100
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#define MAC_CR_ADP BIT(13)
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#define MAC_CR_AUTO_DUPLEX BIT(12)
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#define MAC_CR_AUTO_SPEED BIT(11)
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#define MAC_RX 0x104
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#define MAC_RX_FCS_STRIP BIT(4)
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#define MAC_RX_RXEN BIT(0)
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#define MAC_TX 0x108
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#define MAC_TX_TXEN BIT(0)
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#define FLOW 0x10C
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#define FLOW_CR_TX_FCEN BIT(30)
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#define FLOW_CR_RX_FCEN BIT(29)
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#define RX_ADDRH 0x118
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#define RX_ADDRL 0x11C
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#define MII_ACC 0x120
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#define MII_ACC_MII_READ 0x00000000
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#define MII_ACC_MII_WRITE 0x00000002
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#define MII_ACC_MII_BUSY BIT(0)
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#define MII_DATA 0x124
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#define SS_USB_PKT_SIZE 1024
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#define HS_USB_PKT_SIZE 512
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#define FS_USB_PKT_SIZE 64
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#define MAX_RX_FIFO_SIZE (12 * 1024)
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#define MAX_TX_FIFO_SIZE (12 * 1024)
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#define DEFAULT_BULK_IN_DELAY 0x0800
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#define EEPROM_INDICATOR 0xA5
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#define EEPROM_MAC_OFFSET 0x01
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/* Some extra defines */
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#define LAN7X_INTERNAL_PHY_ID 1
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#define LAN7X_MAC_RX_MAX_SIZE(mtu) \
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((mtu) << 16) /* Max frame size */
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#define LAN7X_MAC_RX_MAX_SIZE_DEFAULT \
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LAN7X_MAC_RX_MAX_SIZE(PKTSIZE_ALIGN + 4 /* VLAN */ + 4 /* CRC */)
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/* Timeouts */
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#define USB_CTRL_SET_TIMEOUT_MS 5000
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#define USB_CTRL_GET_TIMEOUT_MS 5000
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#define USB_BULK_SEND_TIMEOUT_MS 5000
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#define USB_BULK_RECV_TIMEOUT_MS 5000
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#define TIMEOUT_RESOLUTION_MS 50
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#define PHY_CONNECT_TIMEOUT_MS 5000
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#define RX_URB_SIZE 2048
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/* driver private */
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struct lan7x_private {
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struct ueth_data ueth;
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u32 chipid; /* Chip or device ID */
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struct mii_dev *mdiobus;
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struct phy_device *phydev;
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};
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/*
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* Lan7x infrastructure commands
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*/
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int lan7x_write_reg(struct usb_device *udev, u32 index, u32 data);
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int lan7x_read_reg(struct usb_device *udev, u32 index, u32 *data);
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static inline int lan7x_wait_for_bit(struct usb_device *udev,
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const char *prefix, const u32 reg,
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const u32 mask, const bool set,
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const unsigned int timeout_ms,
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const bool breakable)
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{
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u32 val;
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unsigned long start = get_timer(0);
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while (1) {
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lan7x_read_reg(udev, reg, &val);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout_ms)
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break;
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if (breakable && ctrlc()) {
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puts("Abort\n");
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return -EINTR;
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}
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udelay(1);
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WATCHDOG_RESET();
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}
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debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
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mask, set);
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return -ETIMEDOUT;
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}
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int lan7x_mdio_read(struct usb_device *udev, int phy_id, int idx);
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void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx,
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int regval);
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static inline int lan7x_mdio_wait_for_bit(struct usb_device *udev,
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const char *prefix,
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int phy_id, const u32 reg,
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const u32 mask, const bool set,
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const unsigned int timeout_ms,
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const bool breakable)
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{
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u32 val;
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unsigned long start = get_timer(0);
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while (1) {
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val = lan7x_mdio_read(udev, phy_id, reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout_ms)
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break;
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if (breakable && ctrlc()) {
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puts("Abort\n");
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return -EINTR;
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}
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udelay(1);
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WATCHDOG_RESET();
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}
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debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
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mask, set);
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return -ETIMEDOUT;
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}
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int lan7x_phylib_register(struct udevice *udev);
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int lan7x_eth_phylib_connect(struct udevice *udev, struct ueth_data *dev);
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int lan7x_eth_phylib_config_start(struct udevice *udev);
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int lan7x_pmt_phy_reset(struct usb_device *udev,
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struct ueth_data *dev);
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int lan7x_update_flowcontrol(struct usb_device *udev,
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struct ueth_data *dev,
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uint32_t *flow, uint32_t *fct_flow);
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int lan7x_read_eeprom_mac(unsigned char *enetaddr, struct usb_device *udev);
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int lan7x_basic_reset(struct usb_device *udev,
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struct ueth_data *dev);
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void lan7x_eth_stop(struct udevice *dev);
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int lan7x_eth_send(struct udevice *dev, void *packet, int length);
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int lan7x_eth_recv(struct udevice *dev, int flags, uchar **packetp);
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int lan7x_free_pkt(struct udevice *dev, uchar *packet, int packet_len);
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int lan7x_eth_remove(struct udevice *dev);
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