upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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238 lines
6.6 KiB
238 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008 by NXP Semiconductors
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* @Author: Based on code by Kevin Wells
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* @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions
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*
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* Copyright (c) 2015 Tyco Fire Protection Products.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/i2c.h>
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#include <usb.h>
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#include <i2c.h>
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/* OTG I2C controller module register structures */
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struct otgi2c_regs {
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u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */
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u32 otg_i2c_stat; /* OTG I2C Status Register */
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u32 otg_i2c_ctrl; /* OTG I2C Control Register */
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u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */
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u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */
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};
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/* OTG controller module register structures */
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struct otg_regs {
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u32 reserved1[64];
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u32 otg_int_sts; /* OTG int status register */
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u32 otg_int_enab; /* OTG int enable register */
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u32 otg_int_set; /* OTG int set register */
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u32 otg_int_clr; /* OTG int clear register */
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u32 otg_sts_ctrl; /* OTG status/control register */
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u32 otg_timer; /* OTG timer register */
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u32 reserved2[122];
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struct otgi2c_regs otg_i2c;
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u32 reserved3[824];
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u32 otg_clk_ctrl; /* OTG clock control reg */
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u32 otg_clk_sts; /* OTG clock status reg */
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};
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/* otg_sts_ctrl register definitions */
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#define OTG_HOST_EN (1 << 0) /* Enable host mode */
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/* otg_clk_ctrl and otg_clk_sts register definitions */
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#define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */
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#define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */
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#define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */
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#define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */
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/* ISP1301 USB transceiver I2C registers */
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#define MC1_SPEED_REG (1 << 0)
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#define MC1_DAT_SE0 (1 << 2)
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#define MC1_UART_EN (1 << 6)
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#define MC2_SPD_SUSP_CTRL (1 << 1)
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#define MC2_BI_DI (1 << 2)
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#define MC2_PSW_EN (1 << 6)
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#define OTG1_DP_PULLUP (1 << 0)
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#define OTG1_DM_PULLUP (1 << 1)
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#define OTG1_DP_PULLDOWN (1 << 2)
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#define OTG1_DM_PULLDOWN (1 << 3)
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#define OTG1_VBUS_DRV (1 << 5)
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#define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR
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#define ISP1301_I2C_MODE_CONTROL_1_SET 0x04
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#define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05
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#define ISP1301_I2C_MODE_CONTROL_2_SET 0x12
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#define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13
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#define ISP1301_I2C_OTG_CONTROL_1_SET 0x06
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#define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07
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#define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B
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#define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D
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#define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F
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static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
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static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
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static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
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{
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#ifndef CONFIG_DM_I2C
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return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
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#else
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return dm_i2c_write(dev, reg, &value, 1);
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#endif
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}
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static void isp1301_configure(struct udevice *dev)
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{
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#ifndef CONFIG_DM_I2C
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i2c_set_bus_num(I2C_2);
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#endif
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/*
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* LPC32XX only supports DAT_SE0 USB mode
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* This sequence is important
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*/
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/* Disable transparent UART mode first */
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isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
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isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
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isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
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isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
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isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
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MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
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isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
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isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
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isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
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OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
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isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
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OTG1_DM_PULLUP | OTG1_DP_PULLUP);
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isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
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isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
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isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
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/* Enable usb_need_clk clock after transceiver is initialized */
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setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
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}
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static int usbpll_setup(void)
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{
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u32 ret;
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/* make sure clocks are disabled */
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clrbits_le32(&clk_pwr->usb_ctrl,
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CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2);
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/* start PLL clock input */
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setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1);
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/* Setup PLL. */
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setbits_le32(&clk_pwr->usb_ctrl,
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CLK_USBCTRL_FDBK_PLUS1(192 - 1));
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setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
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setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
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ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
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true, CONFIG_SYS_HZ, false);
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if (ret)
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return ret;
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/* enable PLL output */
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setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2);
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return 0;
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}
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int usb_cpu_init(void)
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{
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u32 ret;
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struct udevice *dev = NULL;
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#ifdef CONFIG_DM_I2C
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ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
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if (ret) {
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debug("%s: No bus %d\n", __func__, I2C_2);
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return ret;
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}
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#endif
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/*
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* USB pins routing setup is done by "lpc32xx_usb_init()" and should
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* be call by board "board_init()" or "misc_init_r()" functions.
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*/
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/* enable AHB slave USB clock */
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setbits_le32(&clk_pwr->usb_ctrl,
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CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER);
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/* enable I2C clock */
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writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
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ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
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CONFIG_SYS_HZ, false);
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if (ret)
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return ret;
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/* Configure ISP1301 */
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isp1301_configure(dev);
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/* setup USB clocks and PLL */
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ret = usbpll_setup();
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if (ret)
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return ret;
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/* enable usb_host_need_clk */
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setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN);
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/* enable all needed USB clocks */
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const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN |
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OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
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writel(mask, &otg->otg_clk_ctrl);
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ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true,
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CONFIG_SYS_HZ, false);
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if (ret)
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return ret;
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setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
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isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
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return 0;
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}
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int usb_cpu_stop(void)
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{
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struct udevice *dev = NULL;
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int ret = 0;
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#ifdef CONFIG_DM_I2C
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ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
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if (ret) {
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debug("%s: No bus %d\n", __func__, I2C_2);
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return ret;
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}
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#endif
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/* vbus off */
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isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
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clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
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clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN);
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return ret;
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}
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int usb_cpu_init_fail(void)
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{
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return usb_cpu_stop();
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}
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