upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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411 lines
8.7 KiB
411 lines
8.7 KiB
/*
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* SAMSUNG/GOOGLE Peach-Pit board device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "exynos54xx.dtsi"
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#include <dt-bindings/clock/maxim,max77802.h>
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#include <dt-bindings/regulator/maxim,max77802.h>
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/ {
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model = "Samsung/Google Peach Pit board based on Exynos5420";
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compatible = "google,pit-rev#", "google,pit",
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"google,peach", "samsung,exynos5420", "samsung,exynos5";
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config {
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google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
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hwid = "PIT TEST A-A 7848";
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lazy-init = <1>;
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};
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aliases {
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serial0 = "/serial@12C30000";
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console = "/serial@12C30000";
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pmic = "/i2c@12CA0000";
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i2c104 = &i2c_tunnel;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm 0 1000000 0>;
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brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
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default-brightness-level = <7>;
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power-supply = <&tps65090_fet1>;
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};
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dmc {
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mem-manuf = "samsung";
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mem-type = "ddr3";
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clock-frequency = <800000000>;
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arm-frequency = <900000000>;
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};
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tmu@10060000 {
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samsung,min-temp = <25>;
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samsung,max-temp = <125>;
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samsung,start-warning = <95>;
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samsung,start-tripping = <105>;
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samsung,hw-tripping = <110>;
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samsung,efuse-min-value = <40>;
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samsung,efuse-value = <55>;
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samsung,efuse-max-value = <100>;
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samsung,slope = <274761730>;
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samsung,dc-value = <25>;
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};
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/* MAX77802 is on i2c bus 4 */
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i2c@12CA0000 {
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clock-frequency = <400000>;
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power-regulator@9 {
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compatible = "maxim,max77802-pmic";
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reg = <0x9>;
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};
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};
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i2c@12CD0000 { /* i2c7 */
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clock-frequency = <100000>;
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soundcodec@20 {
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reg = <0x20>;
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compatible = "maxim,max98090-codec";
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};
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edp-lvds-bridge@48 {
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compatible = "parade,ps8625";
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reg = <0x48>;
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sleep-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
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reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>;
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parade,regs = /bits/ 8 <
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0x02 0xa1 0x01 /* HPD low */
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/*
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* SW setting
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* [1:0] SW output 1.2V voltage is lower to 96%
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*/
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0x04 0x14 0x01
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/*
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* RCO SS setting
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* [5:4] = b01 0.5%, b10 1%, b11 1.5%
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*/
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0x04 0xe3 0x20
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0x04 0xe2 0x80 /* [7] RCO SS enable */
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/*
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* RPHY Setting
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* [3:2] CDR tune wait cycle before
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* measure for fine tune b00: 1us,
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* 01: 0.5us, 10:2us, 11:4us.
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*/
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0x04 0x8a 0x0c
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0x04 0x89 0x08 /* [3] RFD always on */
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/*
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* CTN lock in/out:
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* 20000ppm/80000ppm. Lock out 2
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* times.
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*/
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0x04 0x71 0x2d
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/*
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* 2.7G CDR settings
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* NOF=40LSB for HBR CDR setting
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*/
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0x04 0x7d 0x07
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0x04 0x7b 0x00 /* [1:0] Fmin=+4bands */
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0x04 0x7a 0xfd /* [7:5] DCO_FTRNG=+-40% */
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/*
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* 1.62G CDR settings
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* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
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*/
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0x04 0xc0 0x12
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0x04 0xc1 0x92 /* Gitune=-37% */
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0x04 0xc2 0x1c /* Fbstep=100% */
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0x04 0x32 0x80 /* [7]LOS signal disable */
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/*
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* RPIO Setting
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* [7:4] LVDS driver bias current :
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* 75% (250mV swing)
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*/
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0x04 0x00 0xb0
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/*
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* [7:6] Right-bar GPIO output strength is 8mA
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*/
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0x04 0x15 0x40
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/* EQ Training State Machine Setting */
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0x04 0x54 0x10 /* RCO calibration start */
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/* [4:0] MAX_LANE_COUNT set to one lane */
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0x01 0x02 0x81
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/* [4:0] LANE_COUNT_SET set to one lane */
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0x01 0x21 0x81
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0x00 0x52 0x20
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0x00 0xf1 0x03 /* HPD CP toggle enable */
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0x00 0x62 0x41
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/* Counter number add 1ms counter delay */
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0x00 0xf6 0x01
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/*
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* [6]PWM function control by
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* DPCD0040f[7], default is PWM
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* block always works.
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*/
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0x00 0x77 0x06
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/*
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* 04h Adjust VTotal tolerance to
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* fix the 30Hz no display issue
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*/
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0x00 0x4c 0x04
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/* DPCD00400='h00, Parade OUI = 'h001cf8 */
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0x01 0xc0 0x00
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0x01 0xc1 0x1c /* DPCD00401='h1c */
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0x01 0xc2 0xf8 /* DPCD00402='hf8 */
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/*
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* DPCD403~408 = ASCII code
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* D2SLV5='h4432534c5635
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*/
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0x01 0xc3 0x44
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0x01 0xc4 0x32 /* DPCD404 */
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0x01 0xc5 0x53 /* DPCD405 */
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0x01 0xc6 0x4c /* DPCD406 */
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0x01 0xc7 0x56 /* DPCD407 */
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0x01 0xc8 0x35 /* DPCD408 */
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/*
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* DPCD40A, Initial Code major revision
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* '01'
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*/
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0x01 0xca 0x01
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/* DPCD40B Initial Code minor revision '05' */
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0x01 0xcb 0x05
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/* DPCD720 Select internal PWM */
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0x01 0xa5 0xa0
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/*
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* FFh for 100% PWM of brightness, 0h for 0%
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* brightness
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*/
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0x01 0xa7 0xff
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/*
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* Set LVDS output as 6bit-VESA mapping,
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* single LVDS channel
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*/
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0x01 0xcc 0x13
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/* Enable SSC set by register */
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0x02 0xb1 0x20
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/*
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* Set SSC enabled and +/-1% central
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* spreading
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*/
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0x04 0x10 0x16
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/* MPU Clock source: LC => RCO */
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0x04 0x59 0x60
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0x04 0x54 0x14 /* LC -> RCO */
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0x02 0xa1 0x91>; /* HPD high */
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ports {
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port@0 {
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bridge_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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port@1 {
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bridge_in: endpoint {
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remote-endpoint = <&dp_out>;
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};
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};
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};
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};
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};
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sound@3830000 {
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samsung,codec-type = "max98090";
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};
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i2c@12E10000 { /* i2c9 */
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clock-frequency = <400000>;
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tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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};
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};
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panel: panel {
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compatible = "auo,b116xw03";
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power-supply = <&tps65090_fet6>;
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backlight = <&backlight>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&bridge_out>;
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};
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};
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};
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spi@12d30000 { /* spi1 */
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spi-max-frequency = <50000000>;
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firmware_storage_spi: flash@0 {
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compatible = "spi-flash";
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reg = <0>;
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/*
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* A region for the kernel to store a panic event
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* which the firmware will add to the log.
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*/
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elog-panic-event-offset = <0x01e00000 0x100000>;
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elog-shrink-size = <0x400>;
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elog-full-threshold = <0xc00>;
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};
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};
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xhci@12000000 {
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samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
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};
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xhci@12400000 {
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samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
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};
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fimd@14400000 {
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samsung,vl-freq = <60>;
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samsung,vl-col = <1366>;
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samsung,vl-row = <768>;
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samsung,vl-width = <1366>;
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samsung,vl-height = <768>;
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samsung,vl-clkp;
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samsung,vl-dp;
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samsung,vl-bpix = <4>;
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samsung,vl-hspw = <32>;
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samsung,vl-hbpd = <40>;
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samsung,vl-hfpd = <40>;
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samsung,vl-vspw = <6>;
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samsung,vl-vbpd = <10>;
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samsung,vl-vfpd = <12>;
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samsung,vl-cmd-allow-len = <0xf>;
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samsung,winid = <3>;
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samsung,interface-mode = <1>;
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samsung,dp-enabled = <1>;
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samsung,dual-lcd-enabled = <0>;
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};
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};
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&dp {
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status = "okay";
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samsung,color-space = <0>;
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samsung,dynamic-range = <0>;
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samsung,ycbcr-coeff = <0>;
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samsung,color-depth = <1>;
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samsung,link-rate = <0x06>;
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samsung,lane-count = <2>;
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samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
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ports {
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port@0 {
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dp_out: endpoint {
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remote-endpoint = <&bridge_in>;
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};
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};
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};
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};
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&spi_2 {
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spi-max-frequency = <3125000>;
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spi-deactivate-delay = <200>;
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status = "okay";
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num-cs = <1>;
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samsung,spi-src-clk = <0>;
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cs-gpios = <&gpb1 2 0>;
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cros_ec: cros-ec@0 {
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compatible = "google,cros-ec-spi";
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interrupt-parent = <&gpx1>;
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interrupts = <5 0>;
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reg = <0>;
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spi-half-duplex;
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spi-max-timeout-ms = <1100>;
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ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* This describes the flash memory within the EC. Note
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* that the STM32L flash erases to 0, not 0xff.
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*/
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flash@8000000 {
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reg = <0x08000000 0x20000>;
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erase-value = <0>;
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};
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controller-data {
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samsung,spi-feedback-delay = <1>;
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};
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i2c_tunnel: i2c-tunnel {
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compatible = "google,cros-ec-i2c-tunnel";
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#address-cells = <1>;
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#size-cells = <0>;
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google,remote-bus = <0>;
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battery: sbs-battery@b {
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compatible = "sbs,sbs-battery";
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reg = <0xb>;
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sbs,poll-retry-count = <1>;
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sbs,i2c-retry-count = <2>;
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};
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power-regulator@48 {
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compatible = "ti,tps65090";
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reg = <0x48>;
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regulators {
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tps65090_dcdc1: dcdc1 {
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ti,enable-ext-control;
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};
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tps65090_dcdc2: dcdc2 {
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ti,enable-ext-control;
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};
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tps65090_dcdc3: dcdc3 {
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ti,enable-ext-control;
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};
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tps65090_fet1: fet1 {
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regulator-name = "vcd_led";
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};
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tps65090_fet2: fet2 {
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regulator-name = "video_mid";
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regulator-always-on;
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};
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tps65090_fet3: fet3 {
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regulator-name = "wwan_r";
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regulator-always-on;
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};
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tps65090_fet4: fet4 {
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regulator-name = "sdcard";
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regulator-always-on;
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};
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tps65090_fet5: fet5 {
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regulator-name = "camout";
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regulator-always-on;
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};
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tps65090_fet6: fet6 {
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regulator-name = "lcd_vdd";
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};
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tps65090_fet7: fet7 {
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regulator-name = "video_mid_1a";
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regulator-always-on;
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};
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tps65090_ldo1: ldo1 {
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};
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tps65090_ldo2: ldo2 {
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};
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};
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charger {
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compatible = "ti,tps65090-charger";
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};
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};
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};
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};
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};
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#include "cros-ec-keyboard.dtsi"
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