upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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50 lines
1.4 KiB
50 lines
1.4 KiB
/*
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* (C) Copyright 2017 Linaro
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* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __HI3798cv200_H__
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#define __HI3798cv200_H__
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#define REG_BASE_PERI_CTRL 0xF8A20000
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#define REG_BASE_CRG 0xF8A22000
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/* DEVICES */
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#define REG_BASE_MCI 0xF9830000
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#define REG_BASE_UART0 0xF8B00000
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/* PERI control registers (4KB) */
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/* USB2 PHY01 configuration register */
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#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120)
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/* PERI CRG registers (4KB) */
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/* USB2 CTRL0 clock and soft reset */
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#define PERI_CRG46 (REG_BASE_CRG + 0xb8)
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#define USB2_BUS_CKEN (1<<0)
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#define USB2_OHCI48M_CKEN (1<<1)
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#define USB2_OHCI12M_CKEN (1<<2)
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#define USB2_OTG_UTMI_CKEN (1<<3)
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#define USB2_HST_PHY_CKEN (1<<4)
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#define USB2_UTMI0_CKEN (1<<5)
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#define USB2_BUS_SRST_REQ (1<<12)
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#define USB2_UTMI0_SRST_REQ (1<<13)
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#define USB2_HST_PHY_SYST_REQ (1<<16)
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#define USB2_OTG_PHY_SYST_REQ (1<<17)
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#define USB2_CLK48_SEL (1<<20)
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/* USB2 PHY clock and soft reset */
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#define PERI_CRG47 (REG_BASE_CRG + 0xbc)
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#define USB2_PHY01_REF_CKEN (1 << 0)
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#define USB2_PHY2_REF_CKEN (1 << 2)
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#define USB2_PHY01_SRST_REQ (1 << 4)
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#define USB2_PHY2_SRST_REQ (1 << 6)
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#define USB2_PHY01_SRST_TREQ0 (1 << 8)
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#define USB2_PHY01_SRST_TREQ1 (1 << 9)
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#define USB2_PHY2_SRST_TREQ (1 << 10)
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#define USB2_PHY01_REFCLK_SEL (1 << 12)
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#define USB2_PHY2_REFCLK_SEL (1 << 14)
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#endif
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