upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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143 lines
3.6 KiB
143 lines
3.6 KiB
/*
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* Copyright (C) 2012 Vikram Narayananan
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* <vikram186@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <fdtdec.h>
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struct bcm2835_gpios {
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struct bcm2835_gpio_regs *reg;
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struct udevice *pinctrl;
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};
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static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
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{
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struct bcm2835_gpios *gpios = dev_get_priv(dev);
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unsigned val;
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val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
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val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
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val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
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writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
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return 0;
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}
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static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned int gpio,
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int value)
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{
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struct bcm2835_gpios *gpios = dev_get_priv(dev);
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unsigned val;
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gpio_set_value(gpio, value);
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val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
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val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
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val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
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writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
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return 0;
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}
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static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio)
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{
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unsigned val;
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val = readl(&gpios->reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
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return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1;
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}
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static int bcm2835_gpio_get_value(struct udevice *dev, unsigned gpio)
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{
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const struct bcm2835_gpios *gpios = dev_get_priv(dev);
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return bcm2835_get_value(gpios, gpio);
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}
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static int bcm2835_gpio_set_value(struct udevice *dev, unsigned gpio,
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int value)
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{
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struct bcm2835_gpios *gpios = dev_get_priv(dev);
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u32 *output_reg = value ? gpios->reg->gpset : gpios->reg->gpclr;
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writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio),
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&output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]);
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return 0;
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}
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static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct bcm2835_gpios *priv = dev_get_priv(dev);
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int funcid;
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funcid = pinctrl_get_gpio_mux(priv->pinctrl, 0, offset);
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switch (funcid) {
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case BCM2835_GPIO_OUTPUT:
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return GPIOF_OUTPUT;
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case BCM2835_GPIO_INPUT:
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return GPIOF_INPUT;
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default:
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return GPIOF_FUNC;
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}
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}
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static const struct dm_gpio_ops gpio_bcm2835_ops = {
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.direction_input = bcm2835_gpio_direction_input,
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.direction_output = bcm2835_gpio_direction_output,
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.get_value = bcm2835_gpio_get_value,
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.set_value = bcm2835_gpio_set_value,
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.get_function = bcm2835_gpio_get_function,
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};
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static int bcm2835_gpio_probe(struct udevice *dev)
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{
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struct bcm2835_gpios *gpios = dev_get_priv(dev);
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struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_priv->bank_name = "GPIO";
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uc_priv->gpio_count = BCM2835_GPIO_COUNT;
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gpios->reg = (struct bcm2835_gpio_regs *)plat->base;
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/* We know we're spawned by the pinctrl driver */
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gpios->pinctrl = dev->parent;
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return 0;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static int bcm2835_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->base = addr;
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return 0;
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}
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#endif
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U_BOOT_DRIVER(gpio_bcm2835) = {
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.name = "gpio_bcm2835",
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.id = UCLASS_GPIO,
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.ofdata_to_platdata = of_match_ptr(bcm2835_gpio_ofdata_to_platdata),
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.platdata_auto_alloc_size = sizeof(struct bcm2835_gpio_platdata),
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.ops = &gpio_bcm2835_ops,
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.probe = bcm2835_gpio_probe,
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.flags = DM_FLAG_PRE_RELOC,
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.priv_auto_alloc_size = sizeof(struct bcm2835_gpios),
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};
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