upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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92 lines
1.9 KiB
92 lines
1.9 KiB
/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef __PPC__
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/*
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* At least on G2 PowerPC cores, sequential accesses to non-existent
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* memory must be synchronized.
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*/
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# include <asm/io.h> /* for sync() */
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#else
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# define sync() /* nothing */
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#endif
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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long get_ram_size(long *base, long maxsize)
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{
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volatile long *addr;
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long save[32];
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long cnt;
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long val;
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long size;
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int i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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sync ();
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save[i++] = *addr;
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sync ();
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*addr = ~cnt;
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}
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addr = base;
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sync ();
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save[i] = *addr;
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sync ();
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*addr = 0;
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sync ();
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if ((val = *addr) != 0) {
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/* Restore the original data before leaving the function.
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*/
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sync ();
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*addr = save[i];
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for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
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addr = base + cnt;
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sync ();
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*addr = save[--i];
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}
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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size = cnt * sizeof (long);
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/* Restore the original data before leaving the function.
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*/
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for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt;
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*addr = save[--i];
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}
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return (size);
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}
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}
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return (maxsize);
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}
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phys_size_t __weak get_effective_memsize(void)
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{
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#ifndef CONFIG_VERY_BIG_RAM
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return gd->ram_size;
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#else
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/* limit stack to what we can reasonable map */
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return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
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CONFIG_MAX_MEM_MAPPED : gd->ram_size);
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#endif
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}
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