upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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416 lines
12 KiB
416 lines
12 KiB
/*
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* tsec.h
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*
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* Driver for the Motorola Triple Speed Ethernet Controller
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* maintained by Xianghua Xiao (x.xiao@motorola.com)
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* author Andy Fleming
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*
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*/
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#ifndef __TSEC_H
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#define __TSEC_H
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#include <net.h>
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#include <config.h>
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#include <phy.h>
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#include <asm/fsl_enet.h>
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#define TSEC_SIZE 0x01000
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#define TSEC_MDIO_OFFSET 0x01000
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#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
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#define TSEC_GET_REGS(num, offset) \
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(struct tsec __iomem *)\
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(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
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#define TSEC_GET_REGS_BASE(num) \
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TSEC_GET_REGS((num), TSEC_SIZE)
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#define TSEC_GET_MDIO_REGS(num, offset) \
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(struct tsec_mii_mng __iomem *)\
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(CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
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#define TSEC_GET_MDIO_REGS_BASE(num) \
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TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
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#define DEFAULT_MII_NAME "FSL_MDIO"
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#define STD_TSEC_INFO(num) \
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{ \
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.regs = TSEC_GET_REGS_BASE(num), \
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.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
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.devname = CONFIG_TSEC##num##_NAME, \
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.phyaddr = TSEC##num##_PHY_ADDR, \
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.flags = TSEC##num##_FLAGS, \
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.mii_devname = DEFAULT_MII_NAME \
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}
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#define SET_STD_TSEC_INFO(x, num) \
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{ \
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x.regs = TSEC_GET_REGS_BASE(num); \
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x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
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x.devname = CONFIG_TSEC##num##_NAME; \
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x.phyaddr = TSEC##num##_PHY_ADDR; \
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x.flags = TSEC##num##_FLAGS;\
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x.mii_devname = DEFAULT_MII_NAME;\
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}
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#define MAC_ADDR_LEN 6
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/* #define TSEC_TIMEOUT 1000000 */
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#define TSEC_TIMEOUT 1000
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#define TOUT_LOOP 1000000
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/* TBI register addresses */
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#define TBI_CR 0x00
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#define TBI_SR 0x01
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#define TBI_ANA 0x04
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#define TBI_ANLPBPA 0x05
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#define TBI_ANEX 0x06
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#define TBI_TBICON 0x11
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/* TBI MDIO register bit fields*/
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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#define TBICR_ANEG_ENABLE 0x1000
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#define TBICR_RESTART_ANEG 0x0200
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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/* MAC register bits */
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#define MACCFG1_SOFT_RESET 0x80000000
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#define MACCFG1_RESET_RX_MC 0x00080000
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#define MACCFG1_RESET_TX_MC 0x00040000
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#define MACCFG1_RESET_RX_FUN 0x00020000
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#define MACCFG1_RESET_TX_FUN 0x00010000
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#define MACCFG1_LOOPBACK 0x00000100
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#define MACCFG1_RX_FLOW 0x00000020
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#define MACCFG1_TX_FLOW 0x00000010
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#define MACCFG1_SYNCD_RX_EN 0x00000008
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#define MACCFG1_RX_EN 0x00000004
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#define MACCFG1_SYNCD_TX_EN 0x00000002
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#define MACCFG1_TX_EN 0x00000001
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#define MACCFG2_INIT_SETTINGS 0x00007205
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#define MACCFG2_FULL_DUPLEX 0x00000001
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#define MACCFG2_IF 0x00000300
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#define MACCFG2_GMII 0x00000200
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#define MACCFG2_MII 0x00000100
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#define ECNTRL_INIT_SETTINGS 0x00001000
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#define ECNTRL_TBI_MODE 0x00000020
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#define ECNTRL_REDUCED_MODE 0x00000010
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#define ECNTRL_R100 0x00000008
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#define ECNTRL_REDUCED_MII_MODE 0x00000004
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#define ECNTRL_SGMII_MODE 0x00000002
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#ifndef CONFIG_SYS_TBIPA_VALUE
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#define CONFIG_SYS_TBIPA_VALUE 0x1f
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#endif
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#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
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#define MINFLR_INIT_SETTINGS 0x00000040
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#define DMACTRL_INIT_SETTINGS 0x000000c3
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#define DMACTRL_GRS 0x00000010
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#define DMACTRL_GTS 0x00000008
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#define TSTAT_CLEAR_THALT 0x80000000
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#define RSTAT_CLEAR_RHALT 0x00800000
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#define IEVENT_INIT_CLEAR 0xffffffff
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#define IEVENT_BABR 0x80000000
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#define IEVENT_RXC 0x40000000
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#define IEVENT_BSY 0x20000000
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#define IEVENT_EBERR 0x10000000
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#define IEVENT_MSRO 0x04000000
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#define IEVENT_GTSC 0x02000000
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#define IEVENT_BABT 0x01000000
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#define IEVENT_TXC 0x00800000
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#define IEVENT_TXE 0x00400000
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#define IEVENT_TXB 0x00200000
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#define IEVENT_TXF 0x00100000
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#define IEVENT_IE 0x00080000
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#define IEVENT_LC 0x00040000
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#define IEVENT_CRL 0x00020000
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#define IEVENT_XFUN 0x00010000
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#define IEVENT_RXB0 0x00008000
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#define IEVENT_GRSC 0x00000100
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#define IEVENT_RXF0 0x00000080
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#define IMASK_INIT_CLEAR 0x00000000
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#define IMASK_TXEEN 0x00400000
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#define IMASK_TXBEN 0x00200000
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#define IMASK_TXFEN 0x00100000
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#define IMASK_RXFEN0 0x00000080
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/* Default Attribute fields */
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#define ATTR_INIT_SETTINGS 0x000000c0
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#define ATTRELI_INIT_SETTINGS 0x00000000
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/* TxBD status field bits */
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#define TXBD_READY 0x8000
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#define TXBD_PADCRC 0x4000
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#define TXBD_WRAP 0x2000
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#define TXBD_INTERRUPT 0x1000
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#define TXBD_LAST 0x0800
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#define TXBD_CRC 0x0400
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#define TXBD_DEF 0x0200
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#define TXBD_HUGEFRAME 0x0080
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#define TXBD_LATECOLLISION 0x0080
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#define TXBD_RETRYLIMIT 0x0040
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_UNDERRUN 0x0002
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#define TXBD_STATS 0x03ff
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/* RxBD status field bits */
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#define RXBD_EMPTY 0x8000
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#define RXBD_RO1 0x4000
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#define RXBD_WRAP 0x2000
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#define RXBD_INTERRUPT 0x1000
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#define RXBD_LAST 0x0800
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#define RXBD_FIRST 0x0400
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#define RXBD_MISS 0x0100
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#define RXBD_BROADCAST 0x0080
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#define RXBD_MULTICAST 0x0040
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#define RXBD_LARGE 0x0020
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#define RXBD_NONOCTET 0x0010
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#define RXBD_SHORT 0x0008
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#define RXBD_CRCERR 0x0004
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#define RXBD_OVERRUN 0x0002
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#define RXBD_TRUNCATED 0x0001
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#define RXBD_STATS 0x003f
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struct txbd8 {
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer length */
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uint32_t bufptr; /* Buffer Pointer */
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};
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struct rxbd8 {
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer Length */
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uint32_t bufptr; /* Buffer Pointer */
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};
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struct tsec_rmon_mib {
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/* Transmit and Receive Counters */
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u32 tr64; /* Tx/Rx 64-byte Frame Counter */
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u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
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u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
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u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
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u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
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u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
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u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
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/* Receive Counters */
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u32 rbyt; /* Receive Byte Counter */
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u32 rpkt; /* Receive Packet Counter */
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u32 rfcs; /* Receive FCS Error Counter */
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u32 rmca; /* Receive Multicast Packet (Counter) */
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u32 rbca; /* Receive Broadcast Packet */
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u32 rxcf; /* Receive Control Frame Packet */
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u32 rxpf; /* Receive Pause Frame Packet */
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u32 rxuo; /* Receive Unknown OP Code */
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u32 raln; /* Receive Alignment Error */
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u32 rflr; /* Receive Frame Length Error */
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u32 rcde; /* Receive Code Error */
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u32 rcse; /* Receive Carrier Sense Error */
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u32 rund; /* Receive Undersize Packet */
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u32 rovr; /* Receive Oversize Packet */
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u32 rfrg; /* Receive Fragments */
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u32 rjbr; /* Receive Jabber */
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u32 rdrp; /* Receive Drop */
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/* Transmit Counters */
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u32 tbyt; /* Transmit Byte Counter */
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u32 tpkt; /* Transmit Packet */
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u32 tmca; /* Transmit Multicast Packet */
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u32 tbca; /* Transmit Broadcast Packet */
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u32 txpf; /* Transmit Pause Control Frame */
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u32 tdfr; /* Transmit Deferral Packet */
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u32 tedf; /* Transmit Excessive Deferral Packet */
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u32 tscl; /* Transmit Single Collision Packet */
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/* (0x2_n700) */
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u32 tmcl; /* Transmit Multiple Collision Packet */
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u32 tlcl; /* Transmit Late Collision Packet */
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u32 txcl; /* Transmit Excessive Collision Packet */
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u32 tncl; /* Transmit Total Collision */
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u32 res2;
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u32 tdrp; /* Transmit Drop Frame */
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u32 tjbr; /* Transmit Jabber Frame */
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u32 tfcs; /* Transmit FCS Error */
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u32 txcf; /* Transmit Control Frame */
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u32 tovr; /* Transmit Oversize Frame */
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u32 tund; /* Transmit Undersize Frame */
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u32 tfrg; /* Transmit Fragments Frame */
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/* General Registers */
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u32 car1; /* Carry Register One */
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u32 car2; /* Carry Register Two */
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u32 cam1; /* Carry Register One Mask */
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u32 cam2; /* Carry Register Two Mask */
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};
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struct tsec_hash_regs {
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u32 iaddr0; /* Individual Address Register 0 */
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u32 iaddr1; /* Individual Address Register 1 */
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u32 iaddr2; /* Individual Address Register 2 */
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u32 iaddr3; /* Individual Address Register 3 */
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u32 iaddr4; /* Individual Address Register 4 */
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u32 iaddr5; /* Individual Address Register 5 */
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u32 iaddr6; /* Individual Address Register 6 */
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u32 iaddr7; /* Individual Address Register 7 */
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u32 res1[24];
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u32 gaddr0; /* Group Address Register 0 */
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u32 gaddr1; /* Group Address Register 1 */
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u32 gaddr2; /* Group Address Register 2 */
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u32 gaddr3; /* Group Address Register 3 */
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u32 gaddr4; /* Group Address Register 4 */
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u32 gaddr5; /* Group Address Register 5 */
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u32 gaddr6; /* Group Address Register 6 */
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u32 gaddr7; /* Group Address Register 7 */
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u32 res2[24];
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};
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struct tsec {
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/* General Control and Status Registers (0x2_n000) */
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u32 res000[4];
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u32 ievent; /* Interrupt Event */
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u32 imask; /* Interrupt Mask */
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u32 edis; /* Error Disabled */
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u32 res01c;
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u32 ecntrl; /* Ethernet Control */
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u32 minflr; /* Minimum Frame Length */
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u32 ptv; /* Pause Time Value */
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u32 dmactrl; /* DMA Control */
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u32 tbipa; /* TBI PHY Address */
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u32 res034[3];
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u32 res040[48];
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/* Transmit Control and Status Registers (0x2_n100) */
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u32 tctrl; /* Transmit Control */
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u32 tstat; /* Transmit Status */
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u32 res108;
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u32 tbdlen; /* Tx BD Data Length */
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u32 res110[5];
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u32 ctbptr; /* Current TxBD Pointer */
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u32 res128[23];
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u32 tbptr; /* TxBD Pointer */
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u32 res188[30];
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/* (0x2_n200) */
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u32 res200;
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u32 tbase; /* TxBD Base Address */
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u32 res208[42];
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u32 ostbd; /* Out of Sequence TxBD */
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u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
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u32 res2b8[18];
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/* Receive Control and Status Registers (0x2_n300) */
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u32 rctrl; /* Receive Control */
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u32 rstat; /* Receive Status */
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u32 res308;
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u32 rbdlen; /* RxBD Data Length */
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u32 res310[4];
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u32 res320;
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u32 crbptr; /* Current Receive Buffer Pointer */
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u32 res328[6];
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u32 mrblr; /* Maximum Receive Buffer Length */
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u32 res344[16];
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u32 rbptr; /* RxBD Pointer */
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u32 res388[30];
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/* (0x2_n400) */
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u32 res400;
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u32 rbase; /* RxBD Base Address */
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u32 res408[62];
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/* MAC Registers (0x2_n500) */
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u32 maccfg1; /* MAC Configuration #1 */
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u32 maccfg2; /* MAC Configuration #2 */
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u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
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u32 hafdup; /* Half-duplex */
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u32 maxfrm; /* Maximum Frame */
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u32 res514;
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u32 res518;
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u32 res51c;
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u32 resmdio[6];
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u32 res538;
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u32 ifstat; /* Interface Status */
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u32 macstnaddr1; /* Station Address, part 1 */
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u32 macstnaddr2; /* Station Address, part 2 */
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u32 res548[46];
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/* (0x2_n600) */
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u32 res600[32];
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/* RMON MIB Registers (0x2_n680-0x2_n73c) */
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struct tsec_rmon_mib rmon;
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u32 res740[48];
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/* Hash Function Registers (0x2_n800) */
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struct tsec_hash_regs hash;
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u32 res900[128];
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/* Pattern Registers (0x2_nb00) */
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u32 resb00[62];
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u32 attr; /* Default Attribute Register */
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u32 attreli; /* Default Attribute Extract Length and Index */
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/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
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u32 resc00[256];
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};
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#define TSEC_GIGABIT (1 << 0)
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/* These flags currently only have meaning if we're using the eTSEC */
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#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
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#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
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struct tsec_private {
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struct tsec __iomem *regs;
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struct tsec_mii_mng __iomem *phyregs_sgmii;
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struct phy_device *phydev;
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phy_interface_t interface;
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struct mii_dev *bus;
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uint phyaddr;
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char mii_devname[16];
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u32 flags;
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};
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struct tsec_info_struct {
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struct tsec __iomem *regs;
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struct tsec_mii_mng __iomem *miiregs_sgmii;
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char *devname;
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char *mii_devname;
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phy_interface_t interface;
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unsigned int phyaddr;
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u32 flags;
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};
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int tsec_standard_init(bd_t *bis);
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int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
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#endif /* __TSEC_H */
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